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## SLI

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

The following figure shows an example of the operation of shift left by 3 for an 8-bit vector element.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

### Scalar

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | != 0000 | immb | 0 | 1 | 0 | 1 | 0 | 1 | Rn | Rd
|  |  | immh |  |  |  |  |

####

SLI <V><d>, <V><n>, #<shift>

integer d = UInt(Rd); integer n = UInt(Rn); if immh<3> != '1' then UNDEFINED; constant integer esize = 8 << 3; constant integer datasize = esize; integer elements = 1; integer shift = UInt(immh:immb) - esize;

### Vector

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | 0 | != 0000 | immb | 0 | 1 | 0 | 1 | 0 | 1 | Rn | Rd
|  |  |  | immh |  |  |  |  |

####

SLI <Vd>.<T>, <Vn>.<T>, #<shift>

integer d = UInt(Rd); integer n = UInt(Rn); if immh == '0000' then SEE(asimdimm); if immh<3>:Q == '10' then UNDEFINED; constant integer esize = 8 << HighestSetBit(immh); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; integer shift = UInt(immh:immb) - esize;

### Assembler Symbols

<V> | Is a width specifier, encoded in immh:
immh | <V>
--- | ---
0xxx | RESERVED
1xxx | D

<d> | Is the number of the SIMD&FP destination register, in the "Rd" field.

<n> | Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> | Is an arrangement specifier, encoded in immh:Q:
immh | Q | <T>
--- | --- | ---
0000 | x | SEE Advanced SIMD modified immediate
0001 | 0 | 8B
0001 | 1 | 16B
001x | 0 | 4H
001x | 1 | 8H
01xx | 0 | 2S
01xx | 1 | 4S
1xxx | 0 | RESERVED
1xxx | 1 | 2D

<Vn> | Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<shift> | For the scalar variant: is the left shift amount, in the range 0 to 63, encoded in immh:immb:
immh | <shift>
--- | ---
0xxx | RESERVED
1xxx | (UInt(immh:immb)-64)
| For the vector variant: is the left shift amount, in the range 0 to the element width in bits minus 1, encoded in immh:immb:
immh | <shift>
--- | ---
0000 | SEE Advanced SIMD modified immediate
0001 | (UInt(immh:immb)-8)
001x | (UInt(immh:immb)-16)
01xx | (UInt(immh:immb)-32)
1xxx | (UInt(immh:immb)-64)

### Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; bits(datasize) operand2 = V[d, datasize]; bits(datasize) result; bits(esize) mask = LSL(Ones(esize), shift); bits(esize) shifted; for e = 0 to elements-1 shifted = LSL(Elem[operand, e, esize], shift); Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted; V[d, datasize] = result;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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