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## LDRB (register)

Load Register Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, zero-extends it, and writes it to a register. For information about memory accesses, see Load/Store addressing modes.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | Rm | option | S | 1 | 0 | Rn | Rt
size |  |  |  | opc |  |  |  |  |  |  |

#### Extended register (option != 011)

LDRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]

#### Shifted register (option == 011)

LDRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]

if option<1> == '0' then UNDEFINED; // sub-word index ExtendType extend_type = DecodeRegExtend(option);

### Assembler Symbols

<Wt> | Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Wm> | When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field.

<Xm> | When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field.

<extend> | Is the index extend specifier, encoded in option:
option | <extend>
--- | ---
010 | UXTW
110 | SXTW
111 | SXTX

<amount> | Is the index shift amount, it must be #0, encoded in "S" as 0 if omitted, or as 1 if present.

### Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); integer m = UInt(Rm);

### Operation

bits(64) offset = ExtendReg(m, extend_type, 0, 64); bits(64) address; bits(8) data; boolean privileged = PSTATE.EL != EL0; AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, FALSE, privileged, TRUE); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; address = GenerateAddress(address, offset, accdesc); data = Mem[address, 1, accdesc]; X[t, 32] = ZeroExtend(data, 32);

### Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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