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# GITS_TYPER, ITS Type Register

The GITS_TYPER characteristics are:

## Purpose

Specifies the features that an ITS supports.

## Configuration

There are no configuration notes.

## Attributes

GITS_TYPER is a 64-bit register.

## Field descriptions

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | INV | UMSIirq | UMSI | nID | SVPET | VMAPP | VSGI | MPAM | VMOVP | CIL | CIDbits
HCC | RES0 | PTA | SEIS | Devbits | ID_bits | ITT_entry_size | IMPLEMENTATION DEFINED | CCT | Virtual | Physical

#### Bits [63:47]

Reserved, RES0.

#### INV, bit [46]

ITS cache invalidation behavior on disable.

The value of this field is an IMPLEMENTATION DEFINED choice of:

INV | Meaning
--- | ---
0b0 | It is IMPLEMENTATION DEFINED whether ITS caches are invalidated on clearing GITS_CTLR.Enabled and GITS_BASER<n>.Valid.
0b1 | ITS caches are invalidated on clearing GITS_CTLR.Enabled and GITS_BASER<n>.Valid.

If GITS_TYPER.INV is 1, after the following sequence:

- GITS_CTLR.Enabled written to 0.
- A read of GITS_CTLR.Quiescent returns 1.
- GITS_BASER<n>.Valid written to 0.

There is no cached information from the ITS memory structure pointed to by GITS_BASER<n>.

Access to this field is RO.

#### UMSIirq, bit [45]

Indicates support for generating an interrupt on receiving unmapped MSI.

The value of this field is an IMPLEMENTATION DEFINED choice of:

UMSIirq | Meaning
--- | ---
0b0 | Interrupt on unmapped MSI not supported.
0b1 | Interrupt on unmapped MSI is supported.

If GITS_TYPER.UMSI is 0, this field is RES0.

Access to this field is RO.

#### UMSI, bit [44]

Indicates suport for reporting receipt of unmapped MSIs.

The value of this field is an IMPLEMENTATION DEFINED choice of:

UMSI | Meaning
--- | ---
0b0 | Reporting of unmapped MSIs is not supported.
0b1 | Reporting of unmapped MSIs is supported.

Access to this field is RO.

#### nID, bit [43]
When GICv4.1 is implemented:

nID

The value of this field is an IMPLEMENTATION DEFINED choice of:

nID | Meaning
--- | ---
0b0 | Individual doorbell interrupt supported.
0b1 | Individual doorbell interrupt not supported.

Access to this field is RO.

####
Otherwise:

Reserved, RES0.

#### SVPET, bits [42:41]
When GICv4.1 is implemented:

SVPET

The value of this field is an IMPLEMENTATION DEFINED choice of:

SVPET | Meaning
--- | ---
0b00 | vPE Table is not shared with Redistributors.
0b01 | vPE Table is shared with the groups of Redistributors indicated by GITS_MPIDR.Aff3.
0b10 | vPE Table is shared with the groups of Redistributors indicated by GITS_MPIDR fields Aff3 and Aff2.
0b11 | vPE Table is shared with the groups of Redistributors indicated by GITS_MPIDR fields Aff3, Aff2 and Aff1.

Access to this field is RO.

####
Otherwise:

Reserved, RES0.

#### VMAPP, bit [40]
When GICv4.1 is implemented:

VMAPP

The value of this field is an IMPLEMENTATION DEFINED choice of:

VMAPP | Meaning
--- | ---
0b0 | FEAT_GICv4 VMAPP command layout.
0b1 | FEAT_GICv4p1 VMAPP command layout.

Access to this field is RO.

####
Otherwise:

Reserved, RES0.

#### VSGI, bit [39]
When GICv4.1 is implemented:

VSGI

The value of this field is an IMPLEMENTATION DEFINED choice of:

VSGI | Meaning
--- | ---
0b0 | Direct injection of SGIs is not supported.
0b1 | Direct injection of SGIs is supported.

Access to this field is RO.

####
Otherwise:

Reserved, RES0.

#### MPAM, bit [38]
When GICv3.1 is implemented:

MPAM

The value of this field is an IMPLEMENTATION DEFINED choice of:

MPAM | Meaning
--- | ---
0b0 | MPAM is not supported.
0b1 | MPAM is supported.

Access to this field is RO.

####
Otherwise:

Reserved, RES0.

#### VMOVP, bit [37]
When GICv4 is implemented:

Indicates the form of the VMOVP command.

The value of this field is an IMPLEMENTATION DEFINED choice of:

VMOVP | Meaning
--- | ---
0b0 | When moving a vPE, software must issue a VMOVP on all ITSs that have mappings for that vPE. The ITSList and Sequence Number fields in the VMOVP command must ensure synchronization, otherwise behavior is UNPREDICTABLE.
0b1 | When moving a vPE, software must only issue a VMOVP on one of the ITSs that has a mapping for that vPE. The ITSList and Sequence Number fields in the VMOVP command are RES0.

Access to this field is RO.

####
Otherwise:

Reserved, RES0.

#### CIL, bit [36]

Collection ID Limit.

The value of this field is an IMPLEMENTATION DEFINED choice of:

CIL | Meaning
--- | ---
0b0 | ITS supports 16-bit Collection ID, GITS_TYPER.CIDbits is RES0.
0b1 | GITS_TYPER.CIDbits indicates supported Collection ID size

In implementations that do not support Collections in external memory, this bit is RES0 and the number of Collections supported is reported by GITS_TYPER.HCC.

Access to this field is RO.

#### CIDbits, bits [35:32]

Number of Collection ID bits.

- The number of bits of Collection ID minus one.
- When GITS_TYPER.CIL == 0, this field is RES0.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### HCC, bits [31:24]

Hardware Collection Count. The number of interrupt collections supported by the ITS without provisioning of external memory.

Note

Collections held in hardware are unmapped at reset.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### Bits [23:20]

Reserved, RES0.

#### PTA, bit [19]

Physical Target Addresses. Indicates the format of the target address:

The value of this field is an IMPLEMENTATION DEFINED choice of:

PTA | Meaning
--- | ---
0b0 | The target address corresponds to the PE number specified by GICR_TYPER.Processor_Number.
0b1 | The target address corresponds to the base physical address of the required Redistributor.

For more information, see 'RDbase' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).

Access to this field is RO.

#### SEIS, bit [18]

SEI support. Indicates whether the virtual CPU interface supports generation of SEIs:

The value of this field is an IMPLEMENTATION DEFINED choice of:

SEIS | Meaning
--- | ---
0b0 | The ITS does not support local generation of SEIs.
0b1 | The ITS supports local generation of SEIs.

Access to this field is RO.

#### Devbits, bits [17:13]

The number of DeviceID bits implemented, minus one.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### ID_bits, bits [12:8]

The number of EventID bits implemented, minus one.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### ITT_entry_size, bits [7:4]

Read-only. Indicates the number of bytes per translation table entry, minus one.

For more information about the ITS command 'MAPD', see MAPD.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### IMPLEMENTATION DEFINED, bit [3]

IMPLEMENTATION DEFINED.

#### CCT, bit [2]

Cumulative Collection Tables.

The value of this field is an IMPLEMENTATION DEFINED choice of:

CCT | Meaning
--- | ---
0b0 | The total number of supported collections is determined by the number of collections held in memory only.
0b1 | The total number of supported collections is determined by number of collections that are held in memory and the number indicated by GITS_TYPER.HCC.

If GITS_TYPER.HCC == 0, or if memory backed collections are not supported (all GITS_BASER<n>.Type != 100), this bit is RES0.

Access to this field is RO.

#### Virtual, bit [1]
When GICv4 is implemented:

Indicates whether the ITS supports virtual LPIs and direct injection of virtual LPIs:

The value of this field is an IMPLEMENTATION DEFINED choice of:

Virtual | Meaning
--- | ---
0b0 | The ITS does not support virtual LPIs or direct injection of virtual LPIs.
0b1 | The ITS supports virtual LPIs and direct injection of virtual LPIs.

Access to this field is RO.

####
Otherwise:

Reserved, RES0.

#### Physical, bit [0]

Indicates whether the ITS supports physical LPIs:

The value of this field is an IMPLEMENTATION DEFINED choice of:

Physical | Meaning
--- | ---
0b0 | The ITS does not support physical LPIs.
0b1 | The ITS supports physical LPIs.

This field is RES1, indicating that the ITS supports physical LPIs.

Access to this field is RO.

## Accessing GITS_TYPER

#### GITS_TYPER can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
GIC ITS control | 0x0008 | GITS_TYPER

Accesses on this interface are RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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