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# CNTVCTSS, Counter-timer Self-Synchronized Virtual Count register

The CNTVCTSS characteristics are:

## Purpose

Holds the 64-bit virtual count value. The virtual count value is equal to the physical count value visible in CNTPCT minus the virtual offset visible in CNTVOFF.

## Configuration

AArch32 System register CNTVCTSS bits [63:0] are architecturally mapped to AArch64 System register CNTVCTSS_EL0[63:0].

This register is present only when AArch32 is supported and FEAT_ECV is implemented. Otherwise, direct accesses to CNTVCTSS are UNDEFINED.

All reads to the CNTVCTSS occur in program order relative to reads to CNTVCT or CNTVCTSS.

This register is a self-synchronised view of the CNTVCT counter, and cannot be read speculatively.

## Attributes

CNTVCTSS is a 64-bit register.

## Field descriptions

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Self-Synchronized Virtual count value
Self-Synchronized Virtual count value

#### Bits [63:0]

Self-Synchronized Virtual count value.

The reset behavior of this field is:

- On a Warm reset, this field resets to an architecturally UNKNOWN value.

## Accessing CNTVCTSS

Accesses to this register use the following encodings in the System register encoding space:

#### MRRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>

coproc | CRm | opc1
--- | --- | ---
0b1111 | 0b1110 | 0b1001

if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CNTKCTL_EL1.EL0VCTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); else AArch64.AArch32SystemAccessTrap(EL1, 0x04); elsif ELUsingAArch32(EL1) && CNTKCTL.PL0VCTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0VCTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL0) && CNTHCTL_EL2.EL1TVCT == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); else if HaveEL(EL2) && !ELUsingAArch32(EL2) && (!EL2Enabled() || !ELIsInHost(EL0)) then (R[t2], R[t]) = Split(PhysicalCountInt() - CNTVOFF_EL2, 32); elsif HaveEL(EL2) && ELUsingAArch32(EL2) then (R[t2], R[t]) = Split(PhysicalCountInt() - CNTVOFF, 32); else (R[t2], R[t]) = Split(PhysicalCountInt(), 32); elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && CNTHCTL_EL2.EL1TVCT == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); else if HaveEL(EL2) && !ELUsingAArch32(EL2) then (R[t2], R[t]) = Split(PhysicalCountInt() - CNTVOFF_EL2, 32); elsif HaveEL(EL2) && ELUsingAArch32(EL2) then (R[t2], R[t]) = Split(PhysicalCountInt() - CNTVOFF, 32); else (R[t2], R[t]) = Split(PhysicalCountInt(), 32); elsif PSTATE.EL == EL2 then (R[t2], R[t]) = Split(PhysicalCountInt() - CNTVOFF, 32); elsif PSTATE.EL == EL3 then if HaveEL(EL2) then (R[t2], R[t]) = Split(PhysicalCountInt() - CNTVOFF, 32); else (R[t2], R[t]) = Split(PhysicalCountInt(), 32);

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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