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## MOV (element)

Move vector element to another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.

This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

This is an alias of INS (element). This means:

- The encodings in this description are named to match the encodings of INS (element).
- The description of INS (element) gives the operational pseudocode for this instruction.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | imm4 | 1 | Rn | Rd

####

MOV <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]

is equivalent to

INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]

and is always the preferred disassembly.

### Assembler Symbols

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ts> | Is an element size specifier, encoded in imm5:
imm5 | <Ts>
--- | ---
x0000 | RESERVED
xxxx1 | B
xxx10 | H
xx100 | S
x1000 | D

<index1> | Is the destination element index encoded in imm5:
imm5 | <index1>
--- | ---
x0000 | RESERVED
xxxx1 | imm5<4:1>
xxx10 | imm5<4:2>
xx100 | imm5<4:3>
x1000 | imm5<4>

<Vn> | Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<index2> | Is the source element index encoded in imm5:imm4:
imm5 | <index2>
--- | ---
x0000 | RESERVED
xxxx1 | imm4<3:0>
xxx10 | imm4<3:1>
xx100 | imm4<3:2>
x1000 | imm4<3>
Unspecified bits in "imm4" are ignored but should be set to zero by an assembler.

### Operation

The description of INS (element) gives the operational pseudocode for this instruction.

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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