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# TRCDEVTYPE, Trace Device Type Register

The TRCDEVTYPE characteristics are:

## Purpose

Provides discovery information for the component. If the part number field is not recognized, a debugger can report the information that is provided by TRCDEVTYPE about the component instead.

For additional information, see the CoreSight Architecture Specification.

## Configuration

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCDEVTYPE are RES0.

## Attributes

TRCDEVTYPE is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | SUB | MAJOR

#### Bits [31:8]

Reserved, RES0.

#### SUB, bits [7:4]

Component sub-type.

SUB | Meaning
--- | ---
0b0001 | When MAJOR == 0x3 (Trace source): Associated with a PE.

This field reads as 0x1.

Access to this field is RO.

#### MAJOR, bits [3:0]

Component major type.

MAJOR | Meaning
--- | ---
0b0011 | Trace source.

Other values are defined by the CoreSight Architecture.

This field reads as 0x3.

Access to this field is RO.

## Accessing TRCDEVTYPE

External debugger accesses to this register are unaffected by the OS Lock.

#### TRCDEVTYPE can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
ETE | 0xFCC | TRCDEVTYPE

This interface is accessible as follows:

- When !IsTraceCorePowered(), accesses to this register generate an error response.
- Otherwise, accesses to this register are RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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