Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## FRINTM

Multi-vector floating-point round to integral value, toward minus Infinity

Round down to an integral floating-point value, each element of the two or four source vectors, and place the results in the corresponding elements of the two or four destination vectors.

This instruction follows SME2 floating-point numerical behaviors corresponding to instructions that place their results in one or more SVE Z vectors.

This instruction is unpredicated.

It has encodings from 2 classes: Two registers and Four registers

### Two registers
(FEAT_SME2)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | 0 | Zd | 0
| size<1> | size<0> |  |  |  |  |  |  |  |

####

FRINTM { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S }

if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer n = UInt(Zn:'0'); constant integer d = UInt(Zd:'0'); constant integer nreg = 2; constant boolean exact = FALSE; constant FPRounding rounding = FPRounding_NEGINF;

### Four registers
(FEAT_SME2)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | 0 | 0 | Zd | 0 | 0
| size<1> | size<0> |  |  |  |  |  |  |  |

####

FRINTM { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S }

if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer n = UInt(Zn:'00'); constant integer d = UInt(Zd:'00'); constant integer nreg = 4; constant boolean exact = FALSE; constant FPRounding rounding = FPRounding_NEGINF;

### Assembler Symbols

<Zd1> | For the two registers variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.
| For the four registers variant: is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4.

<Zd4> | Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3.

<Zd2> | Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.

<Zn1> | For the two registers variant: is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2.
| For the four registers variant: is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4.

<Zn4> | Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3.

<Zn2> | Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1.

### Operation

CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 32; array [0..3] of bits(VL) results; for r = 0 to nreg-1 constant bits(VL) operand = Z[n+r, VL]; for e = 0 to elements-1 constant bits(32) element = Elem[operand, e, 32]; Elem[results[r], e, 32] = FPRoundInt(element, FPCR, rounding, exact); for r = 0 to nreg-1 Z[d+r, VL] = results[r];

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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