Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## PACIASPPC

Pointer Authentication Code for return address, using key A. This instruction computes and inserts a pointer authentication code for an instruction address, using two modifiers and key A.

The address is in X30.

The first modifier is in SP.

The second modifier is the 64-bit value of PC.

A PACIASPPC instruction has an implicit BTI instruction. The implicit BTI instruction of a PACIASPPC instruction is always compatible with PSTATE.BTYPE == 0b01 and PSTATE.BTYPE == 0b10. Controls in SCTLR_ELx configure whether the implicit BTI instruction of a PACIASPPC instruction is compatible with PSTATE.BTYPE == 0b11. For more information, see PSTATE.BTYPE.

### Integer
(FEAT_PAuth_LR)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0

####

PACIASPPC

if !IsFeatureImplemented(FEAT_PAuth_LR) then UNDEFINED;

### Operation

if IsFeatureImplemented(FEAT_BTI) then // Check for branch target compatibility between PSTATE.BTYPE // and implicit branch target of PACIxSP instruction. SetBTypeCompatible(BTypeCompatible_PACIXSP()); X[30, 64] = AddPACIA2(X[30, 64], SP[], PC64);

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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