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## ADDS (extended register)

Add (extended register), setting flags, adds a register value and a sign or zero-extended register value, followed by an optional left shift amount, and writes the result to the destination register. The argument that is extended from the <Rm> register can be a byte, halfword, word, or doubleword. It updates the condition flags based on the result.

This instruction is used by the alias CMN (extended register).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
sf | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | Rm | option | imm3 | Rn | Rd
| op | S |  |  |  |  |  |  |  |

#### 32-bit (sf == 0)

ADDS <Wd>, <Wn|WSP>, <Wm>{, <extend> {#<amount>}}

#### 64-bit (sf == 1)

ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); constant integer datasize = 32 << UInt(sf); ExtendType extend_type = DecodeRegExtend(option); integer shift = UInt(imm3); if shift > 4 then UNDEFINED;

### Assembler Symbols

<Wd> | Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wn|WSP> | Is the 32-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.

<Wm> | Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.

<Xd> | Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xn|SP> | Is the 64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.

<R> | Is a width specifier, encoded in option:
option | <R>
--- | ---
00x | W
010 | W
x11 | X
10x | W
110 | W

<m> | Is the number [0-30] of the second general-purpose source register or the name ZR (31), encoded in the "Rm" field.

<extend> | For the 32-bit variant: is the extension to be applied to the second source operand, encoded in option:
option | <extend>
--- | ---
000 | UXTB
001 | UXTH
010 | LSL|UXTW
011 | UXTX
100 | SXTB
101 | SXTH
110 | SXTW
111 | SXTX
If "Rn" is '11111' (WSP) and "option" is '010' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTW when "option" is '010'.
| For the 64-bit variant: is the extension to be applied to the second source operand, encoded in option:
option | <extend>
--- | ---
000 | UXTB
001 | UXTH
010 | UXTW
011 | LSL|UXTX
100 | SXTB
101 | SXTH
110 | SXTW
111 | SXTX
If "Rn" is '11111' (SP) and "option" is '011' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTX when "option" is '011'.

<amount> | Is the left shift amount to be applied after extension in the range 0 to 4, defaulting to 0, encoded in the "imm3" field. It must be absent when <extend> is absent, is required when <extend> is LSL, and is optional when <extend> is present but not LSL.

### Alias Conditions

Alias | Is preferred when
--- | ---
CMN (extended register) | Rd == '11111'

### Operation

bits(datasize) result; bits(datasize) operand1 = if n == 31 then SP[]<datasize-1:0> else X[n, datasize]; bits(datasize) operand2 = ExtendReg(m, extend_type, shift, datasize); bits(4) nzcv; (result, nzcv) = AddWithCarry(operand1, operand2, '0'); PSTATE.<N,Z,C,V> = nzcv; X[d, datasize] = result;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

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Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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