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## SUBS (immediate)

Subtract (immediate), setting flags, subtracts an optionally-shifted immediate value from a register value, and writes the result to the destination register. It updates the condition flags based on the result.

This instruction is used by the alias CMP (immediate).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
sf | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | sh | imm12 | Rn | Rd
| op | S |  |  |  |  |

#### 32-bit (sf == 0)

SUBS <Wd>, <Wn|WSP>, #<imm>{, <shift>}

#### 64-bit (sf == 1)

SUBS <Xd>, <Xn|SP>, #<imm>{, <shift>}

integer d = UInt(Rd); integer n = UInt(Rn); integer datasize = if sf == '1' then 64 else 32; bits(datasize) imm; case sh of when '0' imm = ZeroExtend(imm12, datasize); when '1' imm = ZeroExtend(imm12:Zeros(12), datasize);

### Assembler Symbols

<Wd> | Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wn|WSP> | Is the 32-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.

<Xd> | Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xn|SP> | Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.

<imm> | Is an unsigned immediate, in the range 0 to 4095, encoded in the "imm12" field.

<shift> | Is the optional left shift to apply to the immediate, defaulting to LSL #0 and encoded in sh:
sh | <shift>
--- | ---
0 | LSL #0
1 | LSL #12

### Alias Conditions

Alias | Is preferred when
--- | ---
CMP (immediate) | Rd == '11111'

### Operation

bits(datasize) result; bits(datasize) operand1 = if n == 31 then SP[]<datasize-1:0> else X[n, datasize]; bits(datasize) operand2; bits(4) nzcv; operand2 = NOT(imm); (result, nzcv) = AddWithCarry(operand1, operand2, '1'); PSTATE.<N,Z,C,V> = nzcv; X[d, datasize] = result;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.64, AdvSIMD v29.12, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T19:42

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