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# AMEVCNTR1<n>_EL0, Activity Monitors Event Counter Registers 1, n = 0 - 15

The AMEVCNTR1<n>_EL0 characteristics are:

## Purpose

Provides access to the auxiliary activity monitor event counters.

## Configuration

AArch64 System register AMEVCNTR1<n>_EL0 bits [31:0] are architecturally mapped to AArch32 System register AMEVCNTR1<n>[31:0].

AArch64 System register AMEVCNTR1<n>_EL0 bits [63:0] are architecturally mapped to External register AMU.AMEVCNTR1<n>[63:0].

This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMEVCNTR1<n>_EL0 are UNDEFINED.

## Attributes

AMEVCNTR1<n>_EL0 is a 64-bit register.

## Field descriptions

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ACNT
ACNT

#### ACNT, bits [63:0]

Auxiliary activity monitor event counter n.

Value of auxiliary activity monitor event counter n, where n is the number of this register and is a number from 0 to 15.

If all of the following are true, reads of the AMEVCNTR1<n>_EL0 registers from EL0 or EL1 return (PCount<63:0> - AMEVCNTVOFF1<n>_EL2<63:0>), where PCount is the physical count returned when AMEVCNTR1<n>_EL0 is read from EL2 or EL3:

- FEAT_AMUv1p1 is implemented.
- HCR_EL2.AMVOFFEN and SCR_EL3.AMVOFFEN are 1.
- AMCR_EL0.CG1RZ is 0.
- EL2 is implemented and enabled in the current Security state, and the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}.

If the counter is enabled, writes to this register have UNPREDICTABLE results.

The reset behavior of this field is:

- On an AMU reset, this field resets to 0.

## Accessing AMEVCNTR1<n>_EL0

If <n> is greater than or equal to the number of auxiliary activity monitor event counters, reads and writes of AMEVCNTR1<n>_EL0 are UNDEFINED.

Note

AMCGCR_EL0.CG1NC identifies the number of auxiliary activity monitor event counters.

Accesses to this register use the following encodings in the System register encoding space:

#### MRS <Xt>, AMEVCNTR1<m>_EL0 ; Where m = 0-15

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b1101 | 0b110:m[3] | m[2:0]

integer m = UInt(CRm<0>:op2<2:0>); if m >= NUM_AMU_CG1_MONITORS then UNDEFINED; elsif !IsG1ActivityMonitorImplemented(m) then UNDEFINED; elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TAM == '1' then UNDEFINED; elsif AMUSERENR_EL0.EN == '0' then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && CPTR_EL2.TAM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HAFGRTR_EL2.AMEVCNTR1<m>_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif AMCR_EL0.CG1RZ == '1' then X[t, 64] = Zeros(64); else X[t, 64] = AMEVCNTR1_EL0[m]; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TAM == '1' then UNDEFINED; elsif EL2Enabled() && CPTR_EL2.TAM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HAFGRTR_EL2.AMEVCNTR1<m>_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !IsHighestEL(PSTATE.EL) && AMCR_EL0.CG1RZ == '1' then X[t, 64] = Zeros(64); else X[t, 64] = AMEVCNTR1_EL0[m]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3.TAM == '1' then UNDEFINED; elsif HaveEL(EL3) && CPTR_EL3.TAM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif !IsHighestEL(PSTATE.EL) && AMCR_EL0.CG1RZ == '1' then X[t, 64] = Zeros(64); else X[t, 64] = AMEVCNTR1_EL0[m]; elsif PSTATE.EL == EL3 then X[t, 64] = AMEVCNTR1_EL0[m];

#### MSR AMEVCNTR1<m>_EL0, <Xt> ; Where m = 0-15

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b1101 | 0b110:m[3] | m[2:0]

integer m = UInt(CRm<0>:op2<2:0>); if m >= NUM_AMU_CG1_MONITORS then UNDEFINED; elsif !IsG1ActivityMonitorImplemented(m) then UNDEFINED; elsif IsHighestEL(PSTATE.EL) then AMEVCNTR1_EL0[m] = X[t, 64]; else UNDEFINED;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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