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# GICM_TYPER, Distributor MSI Type Register

The GICM_TYPER characteristics are:

## Purpose

Provides information about what features the GIC implementation supports.

## Configuration

This register is available in all configurations of the GIC. When GICD_CTLR.DS==0, this register is Common.

## Attributes

GICM_TYPER is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Valid | CLR | SR | INTID | RES0 | NumSPIs

#### Valid, bit [31]

Reports whether GICM_TYPER content is valid.

The value of this field is an IMPLEMENTATION DEFINED choice of:

Valid | Meaning
--- | ---
0b0 | GICM_TYPER reports no information on the capabilities of the GICM frame, all other fields are RES0.
0b1 | GICM_TYPER reports information on capabilities of GICM frame.

Access to this field is RO.

#### CLR, bit [30]

Reports whether MSI clear registers are supported.

The value of this field is an IMPLEMENTATION DEFINED choice of:

CLR | Meaning
--- | ---
0b0 | MSI clear registers not implemented.
0b1 | MSI clear registers implemented.

Access to this field is RO.

#### SR, bit [29]

Reports whether Secure aliases of MSI registers are supported.

The value of this field is an IMPLEMENTATION DEFINED choice of:

SR | Meaning
--- | ---
0b0 | Secure aliases of MSI registers not implemented.
0b1 | Secure aliases of MSI registers implemented.

Access to this field is RO.

#### INTID, bits [28:16]

INTID of the first SPI assigned to this GICM frame.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### Bits [15:11]

Reserved, RES0.

#### NumSPIs, bits [10:0]

Number of SPIs assigned to this GICM frame.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

## Accessing GICM_TYPER

#### GICM_TYPER can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
GIC Distributor | MSI_base | 0x0004 | GICM_TYPER

Accesses on this interface are RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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