Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## GCSSTR

Guarded Control Stack Store stores a doubleword from a register to memory. The address that is used for the store is calculated from a base register.

### Integer
(FEAT_GCS)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | Rn | Rt
| opc |  |  |

####

GCSSTR <Xt>, [<Xn|SP>]

if !IsFeatureImplemented(FEAT_GCS) then UNDEFINED; integer t = UInt(Rt); integer n = UInt(Rn);

### Assembler Symbols

<Xt> | Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

### Operation

bits(64) address; bits(64) data; bits(2) effective_el = PSTATE.EL; if effective_el == PSTATE.EL then CheckGCSSTREnabled(); boolean privileged = effective_el != EL0; AccessDescriptor accdesc = CreateAccDescGCS(MemOp_STORE, privileged); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; data = X[t, 64]; Mem[address, 8, accdesc] = data;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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