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# TRCIDR4, Trace ID Register 4

The TRCIDR4 characteristics are:

## Purpose

Returns the tracing capabilities of the trace unit.

## Configuration

External register TRCIDR4 bits [31:0] are architecturally mapped to AArch64 System register TRCIDR4[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCIDR4 are RES0.

## Attributes

TRCIDR4 is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUMVMIDC | NUMCIDC | NUMSSCC | NUMRSPAIR | NUMPC | RES0 | SUPPDAC | NUMDVC | NUMACPAIRS

#### NUMVMIDC, bits [31:28]

Indicates the number of Virtual Context Identifier Comparators that are available for tracing.

The value of this field is an IMPLEMENTATION DEFINED choice of:

NUMVMIDC | Meaning
--- | ---
0b0000..0b1000 | The number of Virtual Context Identifier Comparators in this implementation.

All other values are reserved.

Access to this field is RO.

#### NUMCIDC, bits [27:24]

Indicates the number of Context Identifier Comparators that are available for tracing.

The value of this field is an IMPLEMENTATION DEFINED choice of:

NUMCIDC | Meaning
--- | ---
0b0000..0b1000 | The number of Context Identifier Comparators in this implementation.

All other values are reserved.

Access to this field is RO.

#### NUMSSCC, bits [23:20]

Indicates the number of Single-shot Comparator Controls that are available for tracing.

The value of this field is an IMPLEMENTATION DEFINED choice of:

NUMSSCC | Meaning
--- | ---
0b0000..0b1000 | The number of Single-shot Comparator Controls in this implementation.

All other values are reserved.

Access to this field is RO.

#### NUMRSPAIR, bits [19:16]

Indicates the number of resource selector pairs that are available for tracing.

The value of this field is an IMPLEMENTATION DEFINED choice of:

NUMRSPAIR | Meaning
--- | ---
0b0000 | This implementation has zero resource selector pairs.
0b0001..0b1111 | The number of resource selector pairs in this implementation, minus one.

All other values are reserved.

Access to this field is RO.

#### NUMPC, bits [15:12]

Indicates the number of PE Comparator Inputs that are available for tracing.

The value of this field is an IMPLEMENTATION DEFINED choice of:

NUMPC | Meaning
--- | ---
0b0000..0b1000 | The number of PE Comparator Inputs in this implementation.

All other values are reserved.

Access to this field is RO.

#### Bits [11:9]

Reserved, RES0.

#### SUPPDAC, bit [8]
When TRCIDR4.NUMACPAIRS != 0b0000:

Indicates whether data address comparisons are implemented. Data address comparisons are not implemented in ETE and are reserved for other trace architectures. Allocated in other trace architectures.

The value of this field is an IMPLEMENTATION DEFINED choice of:

SUPPDAC | Meaning
--- | ---
0b0 | Data address comparisons not implemented.
0b1 | Data address comparisons implemented.

This field reads as 0b0.

Access to this field is RO.

####
Otherwise:

Reserved, RES0.

#### NUMDVC, bits [7:4]

Indicates the number of data value comparators. Data value comparators are not implemented in ETE and are reserved for other trace architectures. Allocated in other trace architectures.

The value of this field is an IMPLEMENTATION DEFINED choice of:

NUMDVC | Meaning
--- | ---
0b0000..0b1000 | The number of data value comparators in this implementation.

All other values are reserved.

This field reads as 0b0000.

Access to this field is RO.

#### NUMACPAIRS, bits [3:0]

Indicates the number of Address Comparator pairs that are available for tracing.

The value of this field is an IMPLEMENTATION DEFINED choice of:

NUMACPAIRS | Meaning
--- | ---
0b0000..0b1000 | The number of Address Comparator pairs in this implementation.

All other values are reserved.

Access to this field is RO.

## Accessing TRCIDR4

#### TRCIDR4 can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
ETE | 0x1F0 | TRCIDR4

This interface is accessible as follows:

- When OSLockStatus() or !IsTraceCorePowered(), accesses to this register generate an error response.
- Otherwise, accesses to this register are RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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