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# TRCPRGCTLR, Trace Programming Control Register

The TRCPRGCTLR characteristics are:

## Purpose

Enables the trace unit.

## Configuration

External register TRCPRGCTLR bits [31:0] are architecturally mapped to AArch64 System register TRCPRGCTLR[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCPRGCTLR are RES0.

## Attributes

TRCPRGCTLR is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | EN

#### Bits [31:1]

Reserved, RES0.

#### EN, bit [0]

Trace unit enable.

EN | Meaning
--- | ---
0b0 | The trace unit is disabled.
0b1 | The trace unit is enabled.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to 0.

## Accessing TRCPRGCTLR

Must be programmed.

#### TRCPRGCTLR can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
ETE | 0x004 | TRCPRGCTLR

This interface is accessible as follows:

- When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered(), accesses to this register generate an error response.
- Otherwise, accesses to this register are RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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