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# CNTHP_TVAL, Counter-timer Hyp Physical Timer TimerValue register

The CNTHP_TVAL characteristics are:

## Purpose

Holds the timer value for the Hyp mode physical timer.

## Configuration

This register is banked between CNTHP_TVAL and CNTHP_TVAL_S and CNTHP_TVAL_NS.

AArch32 System register CNTHP_TVAL bits [31:0] are architecturally mapped to AArch64 System register CNTHP_TVAL_EL2[31:0].

This register is present only when AArch32 is supported. Otherwise, direct accesses to CNTHP_TVAL are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

## Attributes

CNTHP_TVAL is a 32-bit register.

This register has the following instances:

- CNTHP_TVAL, when EL3 is not implemented.
- CNTHP_TVAL_S, when EL3 is implemented.
- CNTHP_TVAL_NS, when EL3 is implemented.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TimerValue

#### TimerValue, bits [31:0]

The TimerValue view of the EL2 physical timer.

On a read of this register:

- If CNTHP_CTL.ENABLE is 0, the value returned is UNKNOWN.
- If CNTHP_CTL.ENABLE is 1, the value returned is (CNTHP_CVAL - CNTPCT).

On a write of this register, CNTHP_CVAL is set to (CNTPCT + TimerValue), where TimerValue is treated as a signed 32-bit integer.

When CNTHP_CTL.ENABLE is 1, the timer condition is met when (CNTPCT - CNTHP_CVAL) is greater than or equal to zero. This means that TimerValue acts like a 32-bit downcounter timer. When the timer condition is met:

- CNTHP_CTL.ISTATUS is set to 1.
- If CNTHP_CTL.IMASK is 0, an interrupt is generated.

When CNTHP_CTL.ENABLE is 0, the TimerValue cannot be read but continues to decrement. When the timer is enabled, the TimerValue represents the elapsed time whether that time was spent enabled or disabled.

The reset behavior of this field is:

- On a Warm reset, this field resets to an architecturally UNKNOWN value.

## Accessing CNTHP_TVAL

Accesses to this register use the following encodings in the System register encoding space:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b100 | 0b1110 | 0b0010 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if CNTHP_CTL.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTHP_CVAL - PhysicalCountInt())<31:0>; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then UNDEFINED; else if CNTHP_CTL.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTHP_CVAL - PhysicalCountInt())<31:0>;

#### MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b100 | 0b1110 | 0b0010 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then CNTHP_CVAL = SignExtend(R[t], 64) + PhysicalCountInt(); elsif PSTATE.EL == EL3 then if SCR.NS == '0' then UNDEFINED; else CNTHP_CVAL = SignExtend(R[t], 64) + PhysicalCountInt();

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b1110 | 0b0010 | 0b000

if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CNTKCTL_EL1.EL0PTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); else AArch64.AArch32SystemAccessTrap(EL1, 0x03); elsif ELUsingAArch32(EL1) && CNTKCTL.PL0PTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && HCR_EL2.TGE == '0' && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && CNTHCTL.PL1PCEN == '0' then AArch32.TakeHypTrapException(0x03); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then if CNTHPS_CTL_EL2.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTHPS_CVAL_EL2 - PhysicalCountInt())<31:0>; elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then if CNTHP_CTL_EL2.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTHP_CVAL_EL2 - PhysicalCountInt())<31:0>; elsif IsFeatureImplemented(FEAT_ECV) && EL2Enabled() && !ELUsingAArch32(EL2) && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1' && !ELIsInHost(EL0) then if CNTP_CTL.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTP_CVAL - (PhysicalCountInt() - CNTPOFF_EL2))<31:0>; elsif HaveEL(EL3) && ELUsingAArch32(EL3) then if SCR.NS == '1' then if CNTP_CTL_NS.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTP_CVAL_NS - PhysicalCountInt())<31:0>; else if CNTP_CTL_S.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTP_CVAL_S - PhysicalCountInt())<31:0>; else if CNTP_CTL.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTP_CVAL - PhysicalCountInt())<31:0>; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && CNTHCTL.PL1PCEN == '0' then AArch32.TakeHypTrapException(0x03); elsif IsFeatureImplemented(FEAT_ECV) && EL2Enabled() && !ELUsingAArch32(EL2) && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1' then if CNTP_CTL.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTP_CVAL - (PhysicalCountInt() - CNTPOFF_EL2))<31:0>; elsif HaveEL(EL3) && ELUsingAArch32(EL3) then if CNTP_CTL_NS.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTP_CVAL_NS - PhysicalCountInt())<31:0>; else if CNTP_CTL.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTP_CVAL - PhysicalCountInt())<31:0>; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then if CNTP_CTL_NS.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTP_CVAL_NS - PhysicalCountInt())<31:0>; else if CNTP_CTL.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTP_CVAL - PhysicalCountInt())<31:0>; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then if CNTP_CTL_S.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTP_CVAL_S - PhysicalCountInt())<31:0>; else if CNTP_CTL_NS.ENABLE == '0' then R[t] = bits(32) UNKNOWN; else R[t] = (CNTP_CVAL_NS - PhysicalCountInt())<31:0>;

#### MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b1110 | 0b0010 | 0b000

if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CNTKCTL_EL1.EL0PTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); else AArch64.AArch32SystemAccessTrap(EL1, 0x03); elsif ELUsingAArch32(EL1) && CNTKCTL.PL0PTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && HCR_EL2.TGE == '0' && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && CNTHCTL.PL1PCEN == '0' then AArch32.TakeHypTrapException(0x03); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then CNTHPS_CVAL_EL2 = SignExtend(R[t], 64) + PhysicalCountInt(); elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then CNTHP_CVAL_EL2 = SignExtend(R[t], 64) + PhysicalCountInt(); elsif IsFeatureImplemented(FEAT_ECV) && EL2Enabled() && !ELUsingAArch32(EL2) && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1' && !ELIsInHost(EL0) then CNTP_CVAL = (SignExtend(R[t], 64) + PhysicalCountInt()) - CNTPOFF_EL2; elsif HaveEL(EL3) && ELUsingAArch32(EL3) then if SCR.NS == '1' then CNTP_CVAL_NS = SignExtend(R[t], 64) + PhysicalCountInt(); else CNTP_CVAL_S = SignExtend(R[t], 64) + PhysicalCountInt(); else CNTP_CVAL = SignExtend(R[t], 64) + PhysicalCountInt(); elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif ELIsInHost(EL2) && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && CNTHCTL.PL1PCEN == '0' then AArch32.TakeHypTrapException(0x03); elsif IsFeatureImplemented(FEAT_ECV) && EL2Enabled() && !ELUsingAArch32(EL2) && SCR_EL3.ECVEn == '1' && CNTHCTL_EL2.ECV == '1' then CNTP_CVAL = (SignExtend(R[t], 64) + PhysicalCountInt()) - CNTPOFF_EL2; elsif HaveEL(EL3) && ELUsingAArch32(EL3) then CNTP_CVAL_NS = SignExtend(R[t], 64) + PhysicalCountInt(); else CNTP_CVAL = SignExtend(R[t], 64) + PhysicalCountInt(); elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then CNTP_CVAL_NS = SignExtend(R[t], 64) + PhysicalCountInt(); else CNTP_CVAL = SignExtend(R[t], 64) + PhysicalCountInt(); elsif PSTATE.EL == EL3 then if SCR.NS == '0' then CNTP_CVAL_S = SignExtend(R[t], 64) + PhysicalCountInt(); else CNTP_CVAL_NS = SignExtend(R[t], 64) + PhysicalCountInt();

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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