Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## ST64BV

Single-copy Atomic 64-byte Store with status result stores eight 64-bit doublewords from consecutive registers, Xt to X(t+7), to a memory location, and writes the status result of the store to a register. The data that is stored is atomic and is required to be 64-byte aligned.

### Integer
(FEAT_LS64_V)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | Rs | 1 | 0 | 1 | 1 | 0 | 0 | Rn | Rt
size |  | VR |  | A | R |  |  | o3 | opc |  |  |

####

ST64BV <Xs>, <Xt>, [<Xn|SP>]

if !IsFeatureImplemented(FEAT_LS64_V) then UNDEFINED; if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED; integer s = UInt(Rs); integer t = UInt(Rt); integer n = UInt(Rn); boolean tagchecked = n != 31;

### Assembler Symbols

<Xs> | Is the 64-bit name of the general-purpose register into which the status result of this instruction is written, encoded in the "Rs" field. The value returned is: 0xFFFFFFFF_FFFFFFFF If the memory location accessed does not support this instruction. In this case, the value at the memory location is UNKNOWN. != 0xFFFFFFFF_FFFFFFFF If the memory location accessed does support this instruction. In this case, the peripheral that provides the response defines the returned value and provides information on the state of the memory update at the memory location. If XZR is used, then the return value is ignored.

<Xt> | Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

### Operation

CheckST64BVEnabled(); bits(512) data; bits(64) address; bits(64) value; AccessDescriptor accdesc = CreateAccDescLS64(MemOp_STORE, tagchecked); for i = 0 to 7 value = X[t+i, 64]; if BigEndian(accdesc.acctype) then value = BigEndianReverse(value); data<63+64*i : 64*i> = value; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; bits(64) status = MemStore64BWithRet(address, data, accdesc); if s != 31 then X[s, 64] = status;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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