Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## ZIP1, ZIP2 (predicates)

Interleave elements from two half predicates

Interleave alternating elements from the lowest or highest halves of the first and second source predicates and place in elements of the destination predicate. This instruction is unpredicated.

It has encodings from 2 classes: High halves and Low halves

### High halves

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | 0 | Pm | 0 | 1 | 0 | 0 | 0 | 1 | 0 | Pn | 0 | Pd
|  |  |  |  |  |  | H |  |  |  |

####

ZIP2 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>

if !HaveSVE() && !HaveSME() then UNDEFINED; constant integer esize = 8 << UInt(size); integer n = UInt(Pn); integer m = UInt(Pm); integer d = UInt(Pd); integer part = 1;

### Low halves

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | size | 1 | 0 | Pm | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Pn | 0 | Pd
|  |  |  |  |  |  | H |  |  |  |

####

ZIP1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>

if !HaveSVE() && !HaveSME() then UNDEFINED; constant integer esize = 8 << UInt(size); integer n = UInt(Pn); integer m = UInt(Pm); integer d = UInt(Pd); integer part = 0;

### Assembler Symbols

<Pd> | Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<T> | Is the size specifier, encoded in size:
size | <T>
--- | ---
00 | B
01 | H
10 | S
11 | D

<Pn> | Is the name of the first source scalable predicate register, encoded in the "Pn" field.

<Pm> | Is the name of the second source scalable predicate register, encoded in the "Pm" field.

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer pairs = VL DIV (esize * 2); bits(PL) operand1 = P[n, PL]; bits(PL) operand2 = P[m, PL]; bits(PL) result; integer base = part * pairs; for p = 0 to pairs-1 Elem[result, 2*p+0, esize DIV 8] = Elem[operand1, base+p, esize DIV 8]; Elem[result, 2*p+1, esize DIV 8] = Elem[operand2, base+p, esize DIV 8]; P[d, PL] = result;

### Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.64, AdvSIMD v29.12, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T19:42

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