Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## DCPS1

Debug Change PE State to EL1, when executed in Debug state:

- If executed at EL0 changes the current Exception level and SP to EL1 using SP_EL1.
- Otherwise, if executed at ELx, selects SP_ELx.

The target exception level of a DCPS1 instruction is:

- EL1 if the instruction is executed at EL0.
- Otherwise, the Exception level at which the instruction is executed.

When the target Exception level of a DCPS1 instruction is ELx, on executing this instruction:

- ELR_ELx becomes unknown.
- SPSR_ELx becomes unknown.
- ESR_ELx becomes unknown.
- DLR_EL0 and DSPSR_EL0 become unknown.
- The endianness is set according to SCTLR_ELx.EE.

This instruction is undefined at EL0 in Non-secure state if EL2 is implemented and HCR_EL2.TGE == 1.

This instruction is always undefined in Non-debug state.

For more information on the operation of the DCPS<n> instructions, see DCPS.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | imm16 | 0 | 0 | 0 | 0 | 1
|  |  |  | LL

####

DCPS1 {#<imm>}

if !Halted() then UNDEFINED;

### Assembler Symbols

<imm> | Is an optional 16-bit unsigned immediate, in the range 0 to 65535, defaulting to 0 and encoded in the "imm16" field.

### Operation

DCPSInstruction(LL);

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.64, AdvSIMD v29.12, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T19:42

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