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# GICH_ELRSR, Empty List Register Status Register

The GICH_ELRSR characteristics are:

## Purpose

Indicates which List registers contain valid interrupts.

## Configuration

This register is present only when FEAT_GICv3_LEGACY is implemented and EL2 is implemented. Otherwise, direct accesses to GICH_ELRSR are RES0.

This register is available when the GIC implementation supports interrupt virtualization.

## Attributes

GICH_ELRSR is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | Status15 | Status14 | Status13 | Status12 | Status11 | Status10 | Status9 | Status8 | Status7 | Status6 | Status5 | Status4 | Status3 | Status2 | Status1 | Status0

#### Bits [31:16]

Reserved, RES0.

#### Status<n>, bit [n], for n = 15 to 0

Status bit for List register <n>:

Status<n> | Meaning
--- | ---
0b0 | GICH_LR<n>, if implemented, contains a valid interrupt. Using this List register can result in overwriting a valid interrupt.
0b1 | GICH_LR<n> does not contain a valid interrupt. The List register is empty and can be used without overwriting a valid interrupt or losing an EOI maintenance interrupt.

For any GICH_LR<n> register, the corresponding status bit is set to 1 if GICH_LR<n>.State is 0b00 and either:

- GICH_LR<n>.HW == 1.
- GICH_LR<n>.EOI == 0.

The reset behavior of this field is:

- On a Warm reset, this field resets to 1.

## Accessing GICH_ELRSR

This register is used only when System register access is not enabled. When System register access is enabled:

- For AArch32 implementations, ICH_ELRSR provides equivalent functionality.
- For AArch64 implementations, ICH_ELRSR_EL2 provides equivalent functionality.

Bits corresponding to unimplemented List registers are RES0.

#### GICH_ELRSR can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
GIC Virtual interface control | 0x0030 | GICH_ELRSR

This interface is accessible as follows:

- When GICD_CTLR.DS == 0, accesses to this register are RO.
- When an access is Secure, accesses to this register are RO.
- When an access is Non-secure, accesses to this register are RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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