Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## SSHLLT

Signed shift left long by immediate (top)

Shift left by immediate each odd-numbered signed element of the source vector, and place the results in the overlapping double-width elements of the destination vector. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. This instruction is unpredicated.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | tszh | 0 | tszl | imm3 | 1 | 0 | 1 | 0 | 0 | 1 | Zn | Zd
|  |  |  |  |  | U | T |  |

####

SSHLLT <Zd>.<T>, <Zn>.<Tb>, #<const>

if !HaveSVE2() && !HaveSME() then UNDEFINED; bits(3) tsize = tszh:tszl; integer esize; case tsize of when '000' UNDEFINED; when '001' esize = 8; when '01x' esize = 16; when '1xx' esize = 32; integer n = UInt(Zn); integer d = UInt(Zd); integer shift = UInt(tsize:imm3) - esize;

### Assembler Symbols

<Zd> | Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> | Is the size specifier, encoded in tszh:tszl:
tszh | tszl | <T>
--- | --- | ---
0 | 00 | RESERVED
0 | 01 | H
0 | 1x | S
1 | xx | D

<Zn> | Is the name of the source scalable vector register, encoded in the "Zn" field.

<Tb> | Is the size specifier, encoded in tszh:tszl:
tszh | tszl | <Tb>
--- | --- | ---
0 | 00 | RESERVED
0 | 01 | B
0 | 1x | H
1 | xx | S

<const> | Is the immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tsz:imm3".

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV (2 * esize); bits(VL) operand = Z[n, VL]; bits(VL) result; for e = 0 to elements-1 bits(esize) element = Elem[operand, 2*e + 1, esize]; integer shifted_value = SInt(element) << shift; Elem[result, e, 2*esize] = shifted_value<2*esize-1:0>; Z[d, VL] = result;

### Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then when PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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