Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## SM3TT2A

SM3TT2A takes three 128-bit vectors from three source SIMD&FP register and a 2-bit immediate index value, and returns a 128-bit result in the destination SIMD&FP register. It performs a three-way exclusive-OR of the three 32-bit fields held in the upper three elements of the first source vector, and adds the resulting 32-bit value and the following three other 32-bit values:

- The bottom 32-bit element of the first source vector, Vd, that was used for the three-way exclusive-OR.
- The 32-bit element held in the top 32 bits of the second source vector, Vn.
- A 32-bit element indexed out of the third source vector, Vm.

A three-way exclusive-OR is performed of the result of this addition, the result of the addition rotated left by 9, and the result of the addition rotated left by 17. The result of this exclusive-OR is returned as the top element of the returned result. The other elements of this result are taken from elements of the first source vector, with the element returned in bits<63:32> being rotated left by 19.

### Advanced SIMD
(FEAT_SM3)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | Rm | 1 | 0 | imm2 | 1 | 0 | Rn | Rd
|  |  |  | opcode |  |

####

SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>.S[<imm2>]

if !IsFeatureImplemented(FEAT_SM3) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer i = UInt(imm2);

### Assembler Symbols

<Vd> | Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.

<Vn> | Is the name of the second SIMD&FP source register, encoded in the "Rn" field.

<Vm> | Is the name of the third SIMD&FP source register, encoded in the "Rm" field.

<imm2> | Is a 32-bit element indexed out of <Vm>, encoded in "imm2".

### Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(128) Vm = V[m, 128]; bits(128) Vn = V[n, 128]; bits(128) Vd = V[d, 128]; bits(32) Wj; bits(128) result; bits(32) TT2; Wj = Elem[Vm, i, 32]; TT2 = Vd<63:32> EOR (Vd<127:96> EOR Vd<95:64>); TT2 = (TT2+Vd<31:0>+Vn<127:96>+Wj)<31:0>; result<31:0> = Vd<63:32>; result<63:32> = ROL(Vd<95:64>, 19); result<95:64> = Vd<127:96>; result<127:96> = TT2 EOR ROL(TT2, 9) EOR ROL(TT2, 17); V[d, 128] = result;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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