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# CTICHINSTATUS, CTI Channel In Status register

The CTICHINSTATUS characteristics are:

## Purpose

Provides the raw status of the ECT channel inputs to the CTI.

## Configuration

CTICHINSTATUS is in the Debug power domain.

## Attributes

CTICHINSTATUS is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CHIN31 | CHIN30 | CHIN29 | CHIN28 | CHIN27 | CHIN26 | CHIN25 | CHIN24 | CHIN23 | CHIN22 | CHIN21 | CHIN20 | CHIN19 | CHIN18 | CHIN17 | CHIN16 | CHIN15 | CHIN14 | CHIN13 | CHIN12 | CHIN11 | CHIN10 | CHIN9 | CHIN8 | CHIN7 | CHIN6 | CHIN5 | CHIN4 | CHIN3 | CHIN2 | CHIN1 | CHIN0

#### CHIN<n>, bit [n], for n = 31 to 0

Input channel <n> status.

Bits [31:N] are RAZ. N is the number of ECT channels implemented as defined by the CTIDEVID.NUMCHAN field.

CHIN<n> | Meaning
--- | ---
0b0 | Input channel <n> is inactive.
0b1 | Input channel <n> is active.

If the ECT channels do not support multicycle events then it is IMPLEMENTATION DEFINED whether an input channel can be observed as active.

## Accessing CTICHINSTATUS

#### CTICHINSTATUS can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
CTI | 0x138 | CTICHINSTATUS

Accesses on this interface are RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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