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## FMLAL (multiple and indexed vector, FP16 to FP32)

Multi-vector floating-point multiply-add long by indexed element

This half-precision floating-point multiply-add long instruction widens all 16-bit half-precision elements in the one, two, or four first source vectors and the indexed element of the second source vector to single-precision format, then multiplies the corresponding elements and destructively adds these values without intermediate rounding to the overlapping 32-bit single-precision elements of the ZA double-vector groups.

The half-precision elements within the second source vector are specified using a 3-bit immediate index which selects the same element position within each 128-bit vector segment.

The lowest of the two consecutive vector numbers forming the double-vector group within all of, each half of, or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo all, half, or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA double-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

This instruction follows SME ZA-targeting floating-point behaviors.

This instruction is unpredicated.

It has encodings from 3 classes: One ZA double-vector , Two ZA double-vectors and Four ZA double-vectors

### One ZA double-vector
(FEAT_SME2)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | Zm | i3h | Rv | 1 | i3l | Zn | 0 | 0 | off3
|  |  |  |  |  |  |  | S |

####

FMLAL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>]

if !HaveSME2() then UNDEFINED; integer v = UInt('010':Rv); integer n = UInt(Zn); integer m = UInt('0':Zm); integer offset = UInt(off3:'0'); integer index = UInt(i3h:i3l); boolean sub_op = FALSE; constant integer nreg = 1;

### Two ZA double-vectors
(FEAT_SME2)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | Zm | 0 | Rv | 1 | i3h | Zn | 0 | 0 | 0 | i3l | off2
|  |  |  |  |  |  |  |  | S |  |

####

FMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>]

if !HaveSME2() then UNDEFINED; integer v = UInt('010':Rv); integer n = UInt(Zn:'0'); integer m = UInt('0':Zm); integer offset = UInt(off2:'0'); integer index = UInt(i3h:i3l); boolean sub_op = FALSE; constant integer nreg = 2;

### Four ZA double-vectors
(FEAT_SME2)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | Zm | 1 | Rv | 1 | i3h | Zn | 0 | 0 | 0 | 0 | i3l | off2
|  |  |  |  |  |  |  |  | S |  |

####

FMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>]

if !HaveSME2() then UNDEFINED; integer v = UInt('010':Rv); integer n = UInt(Zn:'00'); integer m = UInt('0':Zm); integer offset = UInt(off2:'0'); integer index = UInt(i3h:i3l); boolean sub_op = FALSE; constant integer nreg = 4;

### Assembler Symbols

<Wv> | Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.

<offs1> | For the one ZA double-vector variant: is the first vector select offset, encoded as "off3" field times 2.
| For the four ZA double-vectors and two ZA double-vectors variant: is the first vector select offset, encoded as "off2" field times 2.

<offs2> | For the one ZA double-vector variant: is the second vector select offset, encoded as "off3" field times 2 plus 1.
| For the four ZA double-vectors and two ZA double-vectors variant: is the second vector select offset, encoded as "off2" field times 2 plus 1.

<Zn> | Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zn1> | For the two ZA double-vectors variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 2.
| For the four ZA double-vectors variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 4.

<Zn4> | Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" times 4 plus 3.

<Zn2> | Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" times 2 plus 1.

<Zm> | Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.

<index> | Is the element index, in the range 0 to 7, encoded in the "i3h:i3l" fields.

### Operation

CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 32; integer vectors = VL DIV 8; integer vstride = vectors DIV nreg; integer eltspersegment = 128 DIV 32; bits(32) vbase = X[v, 32]; integer vec = (UInt(vbase) + offset) MOD vstride; bits(VL) result; vec = vec - (vec MOD 2); for r = 0 to nreg-1 bits(VL) operand1 = Z[n+r, VL]; bits(VL) operand2 = Z[m, VL]; for i = 0 to 1 bits(VL) operand3 = ZAvector[vec + i, VL]; for e = 0 to elements-1 integer segmentbase = e - (e MOD eltspersegment); integer s = 2 * segmentbase + index; bits(16) element1 = Elem[operand1, 2 * e + i, 16]; bits(16) element2 = Elem[operand2, s, 16]; bits(32) element3 = Elem[operand3, e, 32]; if sub_op then element1 = FPNeg(element1, FPCR); Elem[result, e, 32] = FPMulAddH_ZA(element3, element1, element2, FPCR); ZAvector[vec + i, VL] = result; vec = vec + vstride;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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