Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2

8-bit floating-point convert to BFloat16 (vector). This instruction converts each 8-bit floating-point element from the lower or upper half of the source vector to BFloat16 while downscaling the value, and places the results in the 16-bit elements of the destination vector. BF1CVTL and BF2CVTL convert the elements from the lower half of the source vector while scaling the values by 2-UInt(FPMR.LSCALE[5:0]) and 2-UInt(FPMR.LSCALE2[5:0]), respectively. BF1CVTL2 and BF2CVTL2 convert the elements from the upper half of the source vector while scaling the values by 2-UInt(FPMR.LSCALE[5:0]) and 2-UInt(FPMR.LSCALE2[5:0]), respectively.

The 8-bit floating-point encoding format for BF1CVTL and BF1CVTL2 is selected by FPMR.F8S1. The 8-bit floating-point encoding format for BF2CVTL and BF2CVTL2 is selected by FPMR.F8S2.

### Advanced SIMD
(FEAT_FP8)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | 1 | x | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | Rn | Rd
|  | U |  | size |  | opcode |  |  |

#### BF1CVTL{2} (size == 10)

BF1CVTL{2} <Vd>.8H, <Vn>.<Ta>

#### BF2CVTL{2} (size == 11)

BF2CVTL{2} <Vd>.8H, <Vn>.<Ta>

if !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; integer n = UInt(Rn); integer d = UInt(Rd); integer part = UInt(Q); constant integer elements = 64 DIV 8; boolean issrc2 = size == '11';

### Assembler Symbols

2 | Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is encoded in Q:
Q | 2
--- | ---
0 | [absent]
1 | [present]

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn> | Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<Ta> | Is an arrangement specifier, encoded in Q:
Q | <Ta>
--- | ---
0 | 8B
1 | 16B

### Operation

CheckFPMREnabled(); CheckFPAdvSIMDEnabled64(); bits(64) operand = Vpart[n, part, 64]; bits(128) result; for e = 0 to elements-1 Elem[result, e, 16] = FP8ConvertBF(Elem[operand, e, 8], issrc2, FPCR, FPMR); V[d, 128] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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