Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## TSTART

This instruction starts a new transaction. If the transaction started successfully, the destination register is set to zero. If the transaction failed or was canceled, then all state modifications that were performed transactionally are discarded and the destination register is written with a non-zero value that encodes the cause of the failure.

### System
(FEAT_TME)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | Rt

####

TSTART <Xt>

if !HaveTME() then UNDEFINED; integer t = UInt(Rt);

### Assembler Symbols

<Xt> | Is the 64-bit name of the general-purpose destination register, encoded in the "Rt" field.

### Operation

CheckTMEEnabled(); boolean IsEL1Regime; bit tme; bit tmt; case PSTATE.EL of when EL0 IsEL1Regime = S1TranslationRegime() == EL1; if IsEL1Regime then tme = SCTLR_EL1.TME0; tmt = SCTLR_EL1.TMT0; else tme = SCTLR_EL2.TME0; tmt = SCTLR_EL2.TMT0; when EL1 tme = SCTLR_EL1.TME; tmt = SCTLR_EL1.TMT; when EL2 tme = SCTLR_EL2.TME; tmt = SCTLR_EL2.TMT; when EL3 tme = SCTLR_EL3.TME; tmt = SCTLR_EL3.TMT; otherwise Unreachable(); enable = tme == '1'; trivial = tmt == '1'; if !enable then TransactionStartTrap(t); elsif trivial then TSTATE.nPC = NextInstrAddr(64); TSTATE.Rt = t; FailTransaction(TMFailure_TRIVIAL, FALSE); elsif HaveSME() && PSTATE.SM == '1' then FailTransaction(TMFailure_ERR, FALSE); elsif TSTATE.depth == 255 then FailTransaction(TMFailure_NEST, FALSE); elsif TSTATE.depth == 0 then TSTATE.nPC = NextInstrAddr(64); TSTATE.Rt = t; ClearExclusiveLocal(ProcessorID()); TakeTransactionCheckpoint(); StartTrackingTransactionalReadsWrites(); TSTATE.depth = TSTATE.depth + 1; X[t, 64] = Zeros(64);

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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