AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# TRCDEVARCH, Trace Device Architecture Register

The TRCDEVARCH characteristics are:

## Purpose

Provides discovery information for the component.

For additional information, see the CoreSight Architecture Specification.

## Configuration

External register TRCDEVARCH bits [31:0] are architecturally mapped to AArch64 System register TRCDEVARCH[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCDEVARCH are RES0.

## Attributes

TRCDEVARCH is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ARCHITECT | PRESENT | REVISION | ARCHVER | ARCHPART

#### ARCHITECT, bits [31:21]

Defines the architect of the component. For Trace, this is Arm Limited.

Bits [31:28] are the JEP106 continuation code, 0b0100.

Bits [27:21] are the JEP106 identification code, 0b0111011.

Reads as 0b01000111011.

Access to this field is RO.

#### PRESENT, bit [20]

DEVARCH present. Indicates that the TRCDEVARCH register is present.

Reads as 0b1.

Access to this field is RO.

#### REVISION, bits [19:16]

Revision. Defines the architecture revision of the component.

The value of this field is an IMPLEMENTATION DEFINED choice of:

REVISION | Meaning
--- | ---
0b0000 | ETEv1.0, FEAT_ETE.
0b0001 | ETEv1.1, FEAT_ETEv1p1.
0b0010 | ETEv1.2, FEAT_ETEv1p2.
0b0011 | ETEv1.3, FEAT_ETEv1p3.

All other values are reserved.

Access to this field is RO.

#### ARCHVER, bits [15:12]

Architecture Version. Defines the architecture version of the component.

ARCHVER | Meaning
--- | ---
0b0101 | ETEv1.

ARCHVER and ARCHPART are also defined as a single field, ARCHID, so that ARCHVER is ARCHID[15:12].

This field reads as 0x5.

Access to this field is RO.

#### ARCHPART, bits [11:0]

Architecture Part. Defines the architecture of the component.

ARCHPART | Meaning
--- | ---
0xA13 | Arm PE trace architecture.

ARCHVER and ARCHPART are also defined as a single field, ARCHID, so that ARCHPART is ARCHID[11:0].

This field reads as 0xA13.

Access to this field is RO.

## Accessing TRCDEVARCH

External debugger accesses to this register are unaffected by the OS Lock.

#### TRCDEVARCH can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
ETE | 0xFBC | TRCDEVARCH

This interface is accessible as follows:

- When !IsTraceCorePowered(), accesses to this register generate an error response.
- Otherwise, accesses to this register are RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.