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## ANDS (shifted register)

Bitwise AND (shifted register), setting flags, performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.

This instruction is used by the alias TST (shifted register).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
sf | 1 | 1 | 0 | 1 | 0 | 1 | 0 | shift | 0 | Rm | imm6 | Rn | Rd
| opc |  |  | N |  |  |  |

#### 32-bit (sf == 0)

ANDS <Wd>, <Wn>, <Wm>{, <shift> #<amount>}

#### 64-bit (sf == 1)

ANDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer datasize = if sf == '1' then 64 else 32; if sf == '0' && imm6<5> == '1' then UNDEFINED; ShiftType shift_type = DecodeShift(shift); integer shift_amount = UInt(imm6);

### Assembler Symbols

<Wd> | Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wn> | Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.

<Wm> | Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.

<Xd> | Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xn> | Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.

<Xm> | Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.

<shift> | Is the optional shift to be applied to the final source, defaulting to LSL and encoded in shift:
shift | <shift>
--- | ---
00 | LSL
01 | LSR
10 | ASR
11 | ROR

<amount> | For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.
| For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field,

### Alias Conditions

Alias | Is preferred when
--- | ---
TST (shifted register) | Rd == '11111'

### Operation

bits(datasize) operand1 = X[n, datasize]; bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize); bits(datasize) result; result = operand1 AND operand2; PSTATE.<N,Z,C,V> = result<datasize-1>:IsZeroBit(result):'00'; X[d, datasize] = result;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

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Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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