Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## FSCALE

Floating-point adjust exponent by vector. This instruction multiplies the floating-point elements of the first source vector by 2.0 to the power of the signed integer values in the corresponding elements of the second source vector, and places the results in the corresponding elements of the destination vector.

It has encodings from 2 classes: Half-precision and Single-precision and double-precision

### Half-precision
(FEAT_FP8)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | Rm | 0 | 0 | 1 | 1 | 1 | 1 | Rn | Rd
|  | U |  | a |  |  |  | opcode |  |  |

####

FSCALE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

if !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; constant integer esize = 16; integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); constant integer datasize = if Q == '1' then 128 else 64; constant integer elements = datasize DIV esize;

### Single-precision and double-precision
(FEAT_FP8)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 1 | 0 | 1 | 1 | 1 | 0 | 1 | x | 1 | Rm | 1 | 1 | 1 | 1 | 1 | 1 | Rn | Rd
|  | U |  | size |  |  | opcode |  |  |

####

FSCALE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

if !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; if Q == '0' && size == '11' then UNDEFINED; constant integer esize = 8 << UInt(size); integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); constant integer datasize = if Q == '1' then 128 else 64; constant integer elements = datasize DIV esize;

### Assembler Symbols

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> | For the half-precision variant: is an arrangement specifier, encoded in Q:
Q | <T>
--- | ---
0 | 4H
1 | 8H
| For the single-precision and double-precision variant: is an arrangement specifier, encoded in size<0>:Q:
size<0> | Q | <T>
--- | --- | ---
0 | 0 | 2S
0 | 1 | 4S
1 | 0 | RESERVED
1 | 1 | 2D

<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm> | Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

### Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n, datasize]; bits(datasize) operand2 = V[m, datasize]; bits(datasize) result; for e = 0 to elements-1 bits(esize) op1 = Elem[operand1, e, esize]; integer op2 = SInt(Elem[operand2, e, esize]); Elem[result, e, esize] = FPScale(op1, op2, FPCR); V[d, datasize] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.