Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## SQABS

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

If overflow occurs with any of the results, those results are saturated. If saturation occurs, the cumulative saturation bit FPSR.QC is set.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

### Scalar

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | size | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | Rn | Rd
| U |  |  |  |  |  |  |

####

SQABS <V><d>, <V><n>

integer d = UInt(Rd); integer n = UInt(Rn); integer esize = 8 << UInt(size); integer datasize = esize; integer elements = 1; boolean neg = (U == '1');

### Vector

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | size | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | Rn | Rd
|  | U |  |  |  |  |  |  |

####

SQABS <Vd>.<T>, <Vn>.<T>

integer d = UInt(Rd); integer n = UInt(Rn); if size:Q == '110' then UNDEFINED; integer esize = 8 << UInt(size); integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean neg = (U == '1');

### Assembler Symbols

<V> | Is a width specifier, encoded in size:
size | <V>
--- | ---
00 | B
01 | H
10 | S
11 | D

<d> | Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n> | Is the number of the SIMD&FP source register, encoded in the "Rn" field.

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> | Is an arrangement specifier, encoded in size:Q:
size | Q | <T>
--- | --- | ---
00 | 0 | 8B
00 | 1 | 16B
01 | 0 | 4H
01 | 1 | 8H
10 | 0 | 2S
10 | 1 | 4S
11 | 0 | RESERVED
11 | 1 | 2D

<Vn> | Is the name of the SIMD&FP source register, encoded in the "Rn" field.

### Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; bits(datasize) result; integer element; boolean sat; for e = 0 to elements-1 element = SInt(Elem[operand, e, esize]); if neg then element = -element; else element = Abs(element); (Elem[result, e, esize], sat) = SignedSatQ(element, esize); if sat then FPSR.QC = '1'; V[d, datasize] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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