Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## SETGPTN, SETGMTN, SETGETN

Memory Set with tag setting, unprivileged and non-temporal. These instructions perform a memory set using the value in the bottom byte of the source register and store an Allocation Tag to memory for each Tag Granule written. The Allocation Tag is calculated from the Logical Address Tag in the register which holds the first address that the set is made to. The prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory: SETGPTN, then SETGMTN, and then SETGETN.

SETGPTN performs some preconditioning of the arguments suitable for using the SETGMTN instruction, and performs an implementation defined amount of the memory set. SETGMTN performs an implementation defined amount of the memory set. SETGETN performs the last part of the memory set.

#### Note

The inclusion of implementation defined amounts of memory set allows some optimization of the size that can be performed.

The architecture supports two algorithms for the memory set: option A and option B. Which algorithm is used is implementation defined.

#### Note

Portable software should not assume that the choice of algorithm is constant.

After execution of SETGPTN, option A (which results in encoding PSTATE.C = 0):

- If Xn<63> == 1, the set size is saturated to 0x7FFFFFFFFFFFFFF0.
- Xd holds the original Xd + saturated Xn.
- Xn holds -1* saturated Xn + an implementation defined number of bytes set.
- PSTATE.{N,Z,V} are set to {0,0,0}.

After execution of SETGPTN, option B (which results in encoding PSTATE.C = 1):

- If Xn<63> == 1, the copy size is saturated to 0x7FFFFFFFFFFFFFF0.
- Xd holds the original Xd + an implementation defined number of bytes set.
- Xn holds the saturated Xn - an implementation defined number of bytes set.
- PSTATE.{N,Z,V} are set to {0,0,0}.

For SETGMTN, option A (encoded by PSTATE.C = 0), the format of the arguments is:

- Xn is treated as a signed 64-bit number.
- Xn holds -1* number of bytes remaining to be set in the memory set in total.
- Xd holds the lowest address that the set is made to -Xn.
- At the end of the instruction, the value of Xn is written back with -1* number of bytes remaining to be set in the memory set in total.

For SETGMTN, option B (encoded by PSTATE.C = 1), the format of the arguments is:

- Xn holds the number of bytes remaining to be set in the memory set in total.
- Xd holds the lowest address that the set is made to.
- At the end of the instruction:
  - the value of Xn is written back with the number of bytes remaining to be set in the memory set in total.
  - the value of Xd is written back with the lowest address that has not been set.

For SETGETN, option A (encoded by PSTATE.C = 0), the format of the arguments is:

- Xn is treated as a signed 64-bit number.
- Xn holds -1* the number of bytes remaining to be set in the memory set in total.
- Xd holds the lowest address that the set is made to -Xn.
- At the end of the instruction, the value of Xn is written back with 0.

For SETGETN, option B (encoded by PSTATE.C = 1), the format of the arguments is:

- Xn holds the number of bytes remaining to be set in the memory set in total.
- Xd holds the lowest address that the set is made to.
- At the end of the instruction:
  - the value of Xn is written back with 0.
  - the value of Xd is written back with the lowest address that has not been set.

### Integer
(FEAT_MOPS)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
sz | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | Rs | x | x | 1 | 1 | 0 | 1 | Rn | Rd
|  |  |  |  |  |  | op2 |  |  |

#### Epilogue (op2 == 1011)

SETGETN [<Xd>]!, <Xn>!, <Xs>

#### Main (op2 == 0111)

SETGMTN [<Xd>]!, <Xn>!, <Xs>

#### Prologue (op2 == 0011)

SETGPTN [<Xd>]!, <Xn>!, <Xs>

if !HaveFeatMOPS() then UNDEFINED; if !HaveMTEExt() then UNDEFINED; if sz != '00' then UNDEFINED; integer d = UInt(Rd); integer s = UInt(Rs); integer n = UInt(Rn); bits(2) options = op2<1:0>; MOPSStage stage; case op2<3:2> of when '00' stage = MOPSStage_Prologue; when '01' stage = MOPSStage_Main; when '10' stage = MOPSStage_Epilogue; otherwise UNDEFINED; if s == n || s == d || n == d then UNDEFINED; if d == 31 || n == 31 then UNDEFINED;

### Assembler Symbols

<Xd> | For the epilogue and main variant: is the 64-bit name of the general-purpose register that holds an encoding of the destination address (an integer multiple of 16) and for option B is updated by the instruction, encoded in the "Rd" field.
| For the prologue variant: is the 64-bit name of the general-purpose register that holds an encoding of the destination address (an integer multiple of 16) and is updated by the instruction, encoded in the "Rd" field.

<Xn> | For the epilogue variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set (an integer multiple of 16) and is set to zero at the end of the instruction, encoded in the "Rn" field.
| For the main variant: is the 64-bit name of the general-purpose register that holds an encoding of the number of bytes to be set (an integer multiple of 16) and is updated by the instruction, encoded in the "Rn" field.
| For the prologue variant: is the 64-bit name of the general-purpose register that holds the number of bytes to be set (an integer multiple of 16) and is updated by the instruction, encoded in the "Rn" field.

<Xs> | For the epilogue variant: is the 64-bit name of the general-purpose register that holds the source data, encoded in the "Rs" field.
| For the main and prologue variant: is the 64-bit name of the general-purpose register that holds the source data in bits<7:0>, encoded in the "Rs" field.

### Operation

CheckMOPSEnabled(); bits(64) toaddress = X[d, 64]; bits(64) setsize = X[n, 64]; bits(8) data = X[s, 8]; bits(4) nzcv = PSTATE.<N,Z,C,V>; bits(64) stagesetsize; boolean is_setg = TRUE; integer B; boolean supports_option_a = SETGOptionA(); boolean privileged; case PSTATE.EL of when EL0 privileged = FALSE; when EL1 if EL2Enabled() && HaveNVExt() && HCR_EL2.<NV,NV1> == '11' then privileged = TRUE; else privileged = options<0> == '0'; when EL2 if HaveVirtHostExt() && HCR_EL2.<E2H,TGE> == '11' then privileged = options<0> == '0'; else privileged = TRUE; when EL3 privileged = TRUE; if HaveUAOExt() && PSTATE.UAO == '1' then privileged = PSTATE.EL != EL0; boolean nontemporal = options<1> == '1'; AccessDescriptor accdesc = CreateAccDescSTGMOPS(privileged, nontemporal); if stage == MOPSStage_Prologue then if setsize<63> == '1' then setsize = 0x7FFFFFFFFFFFFFF0<63:0>; if setsize != Zeros(64) && !IsAligned(toaddress, TAG_GRANULE) then AArch64.Abort(toaddress, AlignmentFault(accdesc)); if !IsAligned(setsize, TAG_GRANULE) then AArch64.Abort(toaddress, AlignmentFault(accdesc)); if supports_option_a then nzcv = '0000'; toaddress = toaddress + setsize; setsize = Zeros(64) - setsize; else nzcv = '0010'; stagesetsize = SETPreSizeChoice(toaddress, setsize, is_setg); assert stagesetsize<63> == setsize<63> || stagesetsize == Zeros(64); assert stagesetsize<3:0> == '0000'; if SInt(setsize) > 0 then assert SInt(stagesetsize) <= SInt(setsize); else assert SInt(stagesetsize) >= SInt(setsize); else bits(64) postsize = SETPostSizeChoice(toaddress, setsize, is_setg); assert postsize<63> == setsize<63> || postsize == Zeros(64); assert postsize<3:0> == '0000'; boolean zero_size_exceptions = MemSetZeroSizeCheck(); // Check if this version is consistent with the state of the call. if zero_size_exceptions || SInt(setsize) != 0 then if supports_option_a then if nzcv<1> == '1' then // PSTATE.C boolean wrong_option = TRUE; boolean from_epilogue = stage == MOPSStage_Epilogue; MismatchedMemSetException(supports_option_a, d, s, n, wrong_option, from_epilogue, options, is_setg); else if nzcv<1> == '0' then // PSTATE.C boolean wrong_option = TRUE; boolean from_epilogue = stage == MOPSStage_Epilogue; MismatchedMemSetException(supports_option_a, d, s, n, wrong_option, from_epilogue, options, is_setg); if stage == MOPSStage_Main then stagesetsize = setsize - postsize; if MemSetParametersIllformedM(toaddress, setsize, is_setg) then boolean wrong_option = FALSE; boolean from_epilogue = FALSE; MismatchedMemSetException(supports_option_a, d, s, n, wrong_option, from_epilogue, options, is_setg); else stagesetsize = postsize; if (setsize != postsize || MemSetParametersIllformedE(toaddress, setsize, is_setg)) then boolean wrong_option = FALSE; boolean from_epilogue = TRUE; MismatchedMemSetException(supports_option_a, d, s, n, wrong_option, from_epilogue, options, is_setg); if setsize != Zeros(64) && !IsAligned(toaddress, TAG_GRANULE) then AArch64.Abort(toaddress, AlignmentFault(accdesc)); if !IsAligned(setsize, TAG_GRANULE) then AArch64.Abort(toaddress, AlignmentFault(accdesc)); integer tagstep; bits(4) tag; bits(64) tagaddr; if supports_option_a then while SInt(stagesetsize) < 0 do // IMP DEF selection of the block size that is worked on. While many // implementations might make this constant, that is not assumed. B = SETSizeChoice(toaddress, setsize, 16); assert B <= -1 * SInt(stagesetsize); assert B<3:0> == '0000'; Mem[toaddress+setsize, B, accdesc] = Replicate(data, B); tagstep = B DIV 16; tag = AArch64.AllocationTagFromAddress(toaddress + setsize); while tagstep > 0 do tagaddr = toaddress + setsize + (tagstep - 1) * 16; AArch64.MemTag[tagaddr, accdesc] = tag; tagstep = tagstep - 1; setsize = setsize + B; stagesetsize = stagesetsize + B; if stage != MOPSStage_Prologue then X[n, 64] = setsize; else while UInt(stagesetsize) > 0 do // IMP DEF selection of the block size that is worked on. While many // implementations might make this constant, that is not assumed. B = SETSizeChoice(toaddress, setsize, 16); assert B <= UInt(stagesetsize); assert B<3:0> == '0000'; Mem[toaddress, B, accdesc] = Replicate(data, B); tagstep = B DIV 16; tag = AArch64.AllocationTagFromAddress(toaddress); while tagstep > 0 do tagaddr = toaddress + (tagstep - 1) * 16; AArch64.MemTag[tagaddr, accdesc] = tag; tagstep = tagstep - 1; toaddress = toaddress + B; setsize = setsize - B; stagesetsize = stagesetsize - B; if stage != MOPSStage_Prologue then X[n, 64] = setsize; X[d, 64] = toaddress; if stage == MOPSStage_Prologue then X[n, 64] = setsize; X[d, 64] = toaddress; PSTATE.<N,Z,C,V> = nzcv;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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