Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## SHA1M

SHA1 hash update (majority).

### Advanced SIMD
(FEAT_SHA1)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | Rm | 0 | 0 | 1 | 0 | 0 | 0 | Rn | Rd
| size |  |  |  | opcode |  |  |

####

SHA1M <Qd>, <Sn>, <Vm>.4S

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if !IsFeatureImplemented(FEAT_SHA1) then UNDEFINED;

### Assembler Symbols

<Qd> | Is the 128-bit name of the SIMD&FP source and destination, encoded in the "Rd" field.

<Sn> | Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rn" field.

<Vm> | Is the name of the third SIMD&FP source register, encoded in the "Rm" field.

### Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(128) x = V[d, 128]; bits(32) y = V[n, 32]; // Note: 32 not 128 bits wide bits(128) w = V[m, 128]; bits(32) t; for e = 0 to 3 t = SHAmajority(x<63:32>, x<95:64>, x<127:96>); y = y + ROL(x<31:0>, 5) + t + Elem[w, e, 32]; x<63:32> = ROL(x<63:32>, 30); <y, x> = ROL(y:x, 32); V[d, 128] = x;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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