Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## SHRNT

Shift right narrow by immediate (top)

Shift each unsigned integer value in the source vector elements right by an immediate value, and place the truncated results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | tszh | 1 | tszl | imm3 | 0 | 0 | 0 | 1 | 0 | 1 | Zn | Zd
|  |  |  |  |  |  | U | R | T |  |

####

SHRNT <Zd>.<T>, <Zn>.<Tb>, #<const>

if !HaveSVE2() && !HaveSME() then UNDEFINED; bits(3) tsize = tszh:tszl; if tsize == '000' then UNDEFINED; constant integer esize = 8 << HighestSetBit(tsize); integer n = UInt(Zn); integer d = UInt(Zd); integer shift = (2 * esize) - UInt(tsize:imm3);

### Assembler Symbols

<Zd> | Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> | Is the size specifier, encoded in tszh:tszl:
tszh | tszl | <T>
--- | --- | ---
0 | 00 | RESERVED
0 | 01 | B
0 | 1x | H
1 | xx | S

<Zn> | Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Tb> | Is the size specifier, encoded in tszh:tszl:
tszh | tszl | <Tb>
--- | --- | ---
0 | 00 | RESERVED
0 | 01 | H
0 | 1x | S
1 | xx | D

<const> | Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV (2 * esize); bits(VL) operand = Z[n, VL]; bits(VL) result = Z[d, VL]; for e = 0 to elements-1 bits(2*esize) element = Elem[operand, e, 2*esize]; integer res = UInt(element) >> shift; Elem[result, 2*e + 1, esize] = res<esize-1:0>; Z[d, VL] = result;

### Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.64, AdvSIMD v29.12, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T19:42

Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.