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# PMCR, Performance Monitors Control Register

The PMCR characteristics are:

## Purpose

Provides details of the Performance Monitors implementation, including the number of counters implemented, and configures and controls the counters.

## Configuration

AArch32 System register PMCR bits [31:0] are architecturally mapped to AArch64 System register PMCR_EL0[31:0].

AArch32 System register PMCR bits [10:0] are architecturally mapped to External register PMU.PMCR_EL0[10:0].

This register is present only when AArch32 is supported and FEAT_PMUv3 is implemented. Otherwise, direct accesses to PMCR are UNDEFINED.

## Attributes

PMCR is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
IMP | IDCODE | N | RES0 | FZO | RES0 | LP | LC | DP | X | D | C | P | E

#### IMP, bits [31:24]
When FEAT_PMUv3p7 is not implemented:

Implementer code.

If this field is zero, then PMCR.IDCODE is RES0 and software must use MIDR to identify the PE.

Otherwise, this field and PMCR.IDCODE identify the PMU implementation to software. The implementer codes are allocated by Arm. A nonzero value has the same interpretation as MIDR.Implementer.

Use of this field is deprecated.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

####
Otherwise:

Reserved, RAZ.

#### IDCODE, bits [23:16]
When PMCR.IMP != 0b00000000:

Identification code. Use of this field is deprecated.

Each implementer must maintain a list of identification codes that are specific to the implementer. A specific implementation is identified by the combination of the implementer code and the identification code.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

####
Otherwise:

Reserved, RES0.

#### N, bits [15:11]

Indicates the number of event counters implemented. This value is in the range of 0b00000-0b11111. If the value is 0b00000, then only PMCCNTR is implemented. If the value is 0b11111, then PMCCNTR and 31 event counters are implemented.

In an implementation that includes EL2:

- If EL2 is using AArch32, reads of this field from Non-secure EL1 and Non-secure EL0 return the value of HDCR.HPMN.

- If EL2 is using AArch64 and is enabled in the current Security state, reads of this field from EL1 and EL0 return the value of MDCR_EL2.HPMN.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### Bit [10]

Reserved, RES0.

#### FZO, bit [9]
When FEAT_PMUv3p7 is implemented:

Freeze-on-overflow.

Stop event counters on overflow.

In the description of this field:

- If EL2 is implemented and is using AArch32, then PMN is HDCR.HPMN.
- If EL2 is implemented and is using AArch64, then PMN is MDCR_EL2.HPMN.
- If EL2 is not implemented, then PMN is PMCR.N.

FZO | Meaning
--- | ---
0b0 | Do not freeze on overflow.
0b1 | Affected event counters do not count when PMOVSR[(PMN-1):0] is nonzero.

The counters affected by this field are:

- If EL2 is implemented, event counters PMEVCNTR<n> for values of n less than PMN. This applies even when EL2 is disabled in the current Security state.
- If EL2 is not implemented, all event counters PMEVCNTR<n>.
- If PMCR.DP is 1, the cycle counter PMCCNTR.

Other event counters are not affected by this field.

When PMCR.DP is 0, PMCCNTR is not affected by this field.

The reset behavior of this field is:

- On a Warm reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bit [8]

Reserved, RES0.

#### LP, bit [7]
When FEAT_PMUv3p5 is implemented:

Long event counter enable.

Determines which event counter bit generates an overflow recorded by PMOVSR[n].

In the description of this field:

- If EL2 is implemented and is using AArch32, then PMN is HDCR.HPMN.
- If EL2 is implemented and is using AArch64, then PMN is MDCR_EL2.HPMN.
- If EL2 is not implemented, then PMN is PMCR.N.

LP | Meaning
--- | ---
0b0 | Affected counters overflow on unsigned overflow of PMEVCNTR<n>[31:0].
0b1 | Affected counters overflow on unsigned overflow of PMEVCNTR<n>[63:0].

The counters affected by this field are:

- If EL2 is implemented, event counters PMEVCNTR<n> for values of n less than PMN. This applies even when EL2 is disabled in the current Security state.
- If EL2 is not implemented, all event counters PMEVCNTR<n>.

Other event counters and PMCCNTR are not affected by this field.

PMEVCNTR<n>[63:32] is not accessible in AArch32 state.

If the highest implemented Exception level is using AArch32, it is IMPLEMENTATION DEFINED whether this field is read/write or RAZ/WI.

The reset behavior of this field is:

- On a Warm reset, this field resets to 0.

####
Otherwise:

Reserved, RES0.

#### LC, bit [6]

Long cycle counter enable. Determines when unsigned overflow is recorded by the cycle counter overflow bit.

LC | Meaning
--- | ---
0b0 | Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR[31:0].
0b1 | Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR[63:0].

Arm deprecates use of PMCR.LC = 0.

The reset behavior of this field is:

- On a Warm reset, this field resets to an architecturally UNKNOWN value.

#### DP, bit [5]
When (FEAT_PMUv3p1 is implemented and EL2 is implemented) or EL3 is implemented:

Disable cycle counter when event counting is prohibited.

DP | Meaning
--- | ---
0b0 | Cycle counting by PMCCNTR is not affected by this mechanism.
0b1 | Cycle counting by PMCCNTR is disabled in prohibited regions and when event counting is frozen: If FEAT_PMUv3p1 is implemented, EL2 is implemented, and HDCR.HPMD is 1, then cycle counting by PMCCNTR is disabled at EL2. If FEAT_PMUv3p7 is implemented, EL3 is implemented and using AArch64, and MDCR_EL3.MPMX is 1, then cycle counting by PMCCNTR is disabled at EL3. If FEAT_PMUv3p7 is implemented and event counting is frozen by PMCR.FZO, then cycle counting by PMCCNTR is disabled. If EL3 is implemented, MDCR_EL3.SPME or SDCR.SPME is 0, and either FEAT_PMUv3p7 is not implemented, EL3 is using AArch32, or MDCR_EL3.MPMX is 0, then cycle counting by PMCCNTR is disabled at EL3 and in Secure state.

The conditions when this field disables the cycle counter are the same as when event counting by an event counter PMEVCNTR<n> is prohibited or frozen, when either EL2 is not implemented or n is less than HDCR.HPMN.

For more information, see 'Prohibiting event and cycle counting'.

The reset behavior of this field is:

- On a Warm reset, this field resets to 0.

####
Otherwise:

Reserved, RES0.

#### X, bit [4]
When the implementation includes a PMU event export bus:

Enable export of events in an IMPLEMENTATION DEFINED PMU event export bus.

X | Meaning
--- | ---
0b0 | Do not export events.
0b1 | Export events where not prohibited.

This field enables the exporting of events over an IMPLEMENTATION DEFINED PMU event export bus to another device, for example to an OPTIONAL trace unit.

No events are exported when counting is prohibited.

This field does not affect the generation of Performance Monitors overflow interrupt requests or signaling to a cross-trigger interface (CTI) that can be implemented as signals exported from the PE.

The reset behavior of this field is:

- On a Warm reset, this field resets to 0.

####
Otherwise:

Reserved, RAZ/WI.

#### D, bit [3]

Clock divider.

D | Meaning
--- | ---
0b0 | When enabled, PMCCNTR counts every clock cycle.
0b1 | When enabled, PMCCNTR counts once every 64 clock cycles.

If PMCR.LC == 1, this bit is ignored and the cycle counter counts every clock cycle.

Arm deprecates use of PMCR.D = 1.

The reset behavior of this field is:

- On a Warm reset, this field resets to 0.

#### C, bit [2]

Cycle counter reset. The effects of writing to this bit are:

C | Meaning
--- | ---
0b0 | No action.
0b1 | Reset PMCCNTR to zero.

Note

Resetting PMCCNTR does not change the cycle counter overflow bit. If FEAT_PMUv3p5 is implemented, the value of PMCR.LC is ignored, and bits [63:0] of the cycle counter are reset.

Access to this field is WO/RAZ.

#### P, bit [1]

Event counter reset.

In the description of this field:

- If EL2 is implemented and is using AArch32, then PMN is HDCR.HPMN.

- If EL2 is implemented and is using AArch64, then PMN is MDCR_EL2.HPMN.

- If EL2 is not implemented, then PMN is PMCR.N.

P | Meaning
--- | ---
0b0 | No action.
0b1 | If n is in the range of affected event counters, resets each event counter PMEVCNTR<n> to zero.

The effects of writing to this bit are:

- If EL2 is implemented and enabled in the current Security state, in EL0 and EL1, and PMN is not 0, then a write of 1 to this bit resets event counters in the range [0 .. (PMN-1)].
- If EL2 is disabled in the current Security state, then a write of 1 to this bit resets all the event counters.
- In EL2 and EL3, a write of 1 to this bit resets all the event counters.
- This field does not affect the operation of other event counters and PMCCNTR.

Note

Resetting the event counters does not change the event counter overflow bits.

If FEAT_PMUv3p5 is implemented, the values of HDCR.HLP and PMCR.LP are ignored and bits [63:0] of all affected event counters are reset.

Access to this field is WO/RAZ.

#### E, bit [0]

Enable.

In the description of this field:

- If EL2 is implemented and is using AArch32, then PMN is HDCR.HPMN.
- If EL2 is implemented and is using AArch64, then PMN is MDCR_EL2.HPMN.
- If EL2 is not implemented, then PMN is PMCR.N.

E | Meaning
--- | ---
0b0 | Affected counters are disabled and do not count.
0b1 | Affected counters are enabled by PMCNTENSET.

The counters affected by this field are:

- If EL2 is implemented, event counters PMEVCNTR<n> for values of n less than PMN. This applies even when EL2 is disabled in the current Security state.
- If EL2 is not implemented, all event counters PMEVCNTR<n>.
- The cycle counter PMCCNTR.

Other event counters are not affected by this field.

The reset behavior of this field is:

- On a Warm reset, this field resets to 0.

## Accessing PMCR

Accesses to this register use the following encodings in the System register encoding space:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b1001 | 0b1100 | 0b000

if PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif !ELUsingAArch32(EL1) && (PMUSERENR_EL0.EN == '0' || (IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.UEN == '1')) then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); else AArch64.AArch32SystemAccessTrap(EL1, 0x03); elsif ELUsingAArch32(EL1) && PMUSERENR.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL0) && HSTR_EL2.T9 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T9 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPMCR == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPMCR == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else R[t] = PMCR; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T9 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T9 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPMCR == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPMCR == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else R[t] = PMCR; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else R[t] = PMCR; elsif PSTATE.EL == EL3 then R[t] = PMCR;

#### MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b000 | 0b1001 | 0b1100 | 0b000

if PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif !ELUsingAArch32(EL1) && (PMUSERENR_EL0.EN == '0' || (IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.UEN == '1')) then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); else AArch64.AArch32SystemAccessTrap(EL1, 0x03); elsif ELUsingAArch32(EL1) && PMUSERENR.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL0) && HSTR_EL2.T9 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T9 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMCR_EL0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPMCR == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPMCR == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMCR = R[t]; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T9 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T9 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPMCR == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPMCR == '1' then AArch32.TakeHypTrapException(0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMCR = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMCR = R[t]; elsif PSTATE.EL == EL3 then PMCR = R[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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