Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## SQCADD

Saturating complex integer add with rotate

Add the real and imaginary components of the integral complex numbers from the first source vector to the complex numbers from the second source vector which have first been rotated by 90 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation, equivalent to multiplying the complex numbers in the second source vector by ±j beforehand. Destructively place the results in the corresponding elements of the first source vector. Each result element is saturated to the N-bit element's signed integer range -2(N-1) to (2(N-1) )-1. This instruction is unpredicated.

Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | size | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | rot | Zm | Zdn

####

SQCADD <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>

if !HaveSVE2() && !HaveSME() then UNDEFINED; constant integer esize = 8 << UInt(size); integer m = UInt(Zm); integer dn = UInt(Zdn); boolean sub_i = (rot == '0'); boolean sub_r = (rot == '1');

### Assembler Symbols

<Zdn> | Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.

<T> | Is the size specifier, encoded in size:
size | <T>
--- | ---
00 | B
01 | H
10 | S
11 | D

<Zm> | Is the name of the second source scalable vector register, encoded in the "Zm" field.

<const> | Is the const specifier, encoded in rot:
rot | <const>
--- | ---
0 | #90
1 | #270

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer pairs = VL DIV (2 * esize); bits(VL) operand1 = Z[dn, VL]; bits(VL) operand2 = Z[m, VL]; bits(VL) result; for p = 0 to pairs-1 integer acc_r = SInt(Elem[operand1, 2 * p + 0, esize]); integer acc_i = SInt(Elem[operand1, 2 * p + 1, esize]); integer elt2_r = SInt(Elem[operand2, 2 * p + 0, esize]); integer elt2_i = SInt(Elem[operand2, 2 * p + 1, esize]); if sub_i then acc_r = acc_r - elt2_i; acc_i = acc_i + elt2_r; if sub_r then acc_r = acc_r + elt2_i; acc_i = acc_i - elt2_r; Elem[result, 2 * p + 0, esize] = SignedSat(acc_r, esize); Elem[result, 2 * p + 1, esize] = SignedSat(acc_i, esize); Z[dn, VL] = result;

### Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:

- The MOVPRFX instruction must be unpredicated.
- The MOVPRFX instruction must specify the same destination register as this instruction.
- The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.64, AdvSIMD v29.12, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T19:42

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