Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## CASP, CASPA, CASPAL, CASPL

Compare and Swap Pair of words or doublewords in memory reads a pair of 32-bit words or 64-bit doublewords from memory, and compares them against the values held in the first pair of registers. If the comparison is equal, the values in the second pair of registers are written to memory. If the writes are performed, the reads and writes occur atomically such that no other modification of the memory location can take place between the reads and writes.

- CASPA and CASPAL load from memory with acquire semantics.
- CASPL and CASPAL store to memory with release semantics.
- CASP has neither acquire nor release semantics.

For more information about memory ordering semantics, see Load-Acquire, Store-Release.

For information about addressing modes, see Load/Store addressing modes.

The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails.

If the instruction generates a synchronous Data Abort, the registers which are compared and loaded, that is <Ws> and <W(s+1)>, or <Xs> and <X(s+1)>, are restored to the values held in the registers before the instruction was executed.

### No offset
(FEAT_LSE)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | sz | 0 | 0 | 1 | 0 | 0 | 0 | 0 | L | 1 | Rs | o0 | 1 | 1 | 1 | 1 | 1 | Rn | Rt
|  |  |  |  |  |  | Rt2 |  |

#### 32-bit CASP (sz == 0 && L == 0 && o0 == 0)

CASP <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}]

#### 32-bit CASPA (sz == 0 && L == 1 && o0 == 0)

CASPA <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}]

#### 32-bit CASPAL (sz == 0 && L == 1 && o0 == 1)

CASPAL <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}]

#### 32-bit CASPL (sz == 0 && L == 0 && o0 == 1)

CASPL <Ws>, <W(s+1)>, <Wt>, <W(t+1)>, [<Xn|SP>{, #0}]

#### 64-bit CASP (sz == 1 && L == 0 && o0 == 0)

CASP <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}]

#### 64-bit CASPA (sz == 1 && L == 1 && o0 == 0)

CASPA <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}]

#### 64-bit CASPAL (sz == 1 && L == 1 && o0 == 1)

CASPAL <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}]

#### 64-bit CASPL (sz == 1 && L == 0 && o0 == 1)

CASPL <Xs>, <X(s+1)>, <Xt>, <X(t+1)>, [<Xn|SP>{, #0}]

if !IsFeatureImplemented(FEAT_LSE) then UNDEFINED; if Rs<0> == '1' then UNDEFINED; if Rt<0> == '1' then UNDEFINED; integer s = UInt(Rs); integer t = UInt(Rt); integer n = UInt(Rn); constant integer datasize = 32 << UInt(sz); boolean acquire = L == '1'; boolean release = o0 == '1'; boolean tagchecked = n != 31;

### Assembler Symbols

<Ws> | Is the 32-bit name of the first general-purpose register to be compared and loaded, encoded in the "Rs" field. <Ws> must be an even-numbered register.

<W(s+1)> | Is the 32-bit name of the second general-purpose register to be compared and loaded.

<Wt> | Is the 32-bit name of the first general-purpose register to be conditionally stored, encoded in the "Rt" field. <Wt> must be an even-numbered register.

<W(t+1)> | Is the 32-bit name of the second general-purpose register to be conditionally stored.

<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xs> | Is the 64-bit name of the first general-purpose register to be compared and loaded, encoded in the "Rs" field. <Xs> must be an even-numbered register.

<X(s+1)> | Is the 64-bit name of the second general-purpose register to be compared and loaded.

<Xt> | Is the 64-bit name of the first general-purpose register to be conditionally stored, encoded in the "Rt" field. <Xt> must be an even-numbered register.

<X(t+1)> | Is the 64-bit name of the second general-purpose register to be conditionally stored.

### Operation

bits(64) address; bits(2*datasize) comparevalue; bits(2*datasize) newvalue; bits(2*datasize) data; bits(datasize) s1 = X[s, datasize]; bits(datasize) s2 = X[s+1, datasize]; bits(datasize) t1 = X[t, datasize]; bits(datasize) t2 = X[t+1, datasize]; AccessDescriptor accdesc = CreateAccDescAtomicOp(MemAtomicOp_CAS, acquire, release, tagchecked); comparevalue = if BigEndian(accdesc.acctype) then s1:s2 else s2:s1; newvalue = if BigEndian(accdesc.acctype) then t1:t2 else t2:t1; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; data = MemAtomic(address, comparevalue, newvalue, accdesc); if BigEndian(accdesc.acctype) then X[s, datasize] = data<2*datasize-1:datasize>; X[s+1, datasize] = data<datasize-1:0>; else X[s, datasize] = data<datasize-1:0>; X[s+1, datasize] = data<2*datasize-1:datasize>;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.