Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## BFCVT

Floating-point convert from single-precision to BFloat16 format (scalar) converts the single-precision floating-point value in the 32-bit SIMD&FP source register to BFloat16 format and writes the result in the 16-bit SIMD&FP destination register.

ID_AA64ISAR1_EL1.BF16 indicates whether this instruction is supported.

### Single-precision to BFloat16
(FEAT_BF16)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | Rn | Rd

####

BFCVT <Hd>, <Sn>

if !HaveBF16Ext() then UNDEFINED; integer n = UInt(Rn); integer d = UInt(Rd);

### Assembler Symbols

<Hd> | Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Sn> | Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.

### Operation

CheckFPEnabled64(); bits(32) operand = V[n, 32]; FPCRType fpcr = FPCR[]; boolean merge = IsMerging(fpcr); bits(128) result = if merge then V[d, 128] else Zeros(128); Elem[result, 0, 16] = FPConvertBF(operand, fpcr); V[d, 128] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.64, AdvSIMD v29.12, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T19:42

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