Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## FRINT64X (scalar)

Floating-point Round to 64-bit Integer, using current rounding mode (scalar). This instruction rounds a floating-point value in the SIMD&FP source register to an integral floating-point value that fits into a 64-bit integer size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.

A zero input returns a zero result with the same sign. When the result value is not numerically equal to the input value, an Inexact exception is raised. When the input is infinite, NaN or out-of-range, the instruction returns {for the corresponding result value} the most negative integer representable in the destination size, and an Invalid Operation floating-point exception is raised.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

### Floating-point
(FEAT_FRINTTS)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | x | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | Rn | Rd
|  |  |  | ftype |  |  | op |  |  |

#### Single-precision (ftype == 00)

FRINT64X <Sd>, <Sn>

#### Double-precision (ftype == 01)

FRINT64X <Dd>, <Dn>

if !IsFeatureImplemented(FEAT_FRINTTS) then UNDEFINED; if ftype IN {'1x'} then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 32 << UInt(ftype); constant integer intsize = 32 << 1; FPRounding rounding = FPRoundingMode(FPCR);

### Assembler Symbols

<Dd> | Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Dn> | Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<Sd> | Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Sn> | Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field.

### Operation

CheckFPEnabled64(); boolean merge = IsMerging(FPCR); bits(128) result = if merge then V[d, 128] else Zeros(128); bits(esize) operand = V[n, esize]; Elem[result, 0, esize] = FPRoundIntN(operand, FPCR, rounding, intsize); V[d, 128] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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