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## DECD, DECH, DECW (vector)

Decrement vector by multiple of predicate constraint element count

Determines the number of active elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then uses the result to decrement all destination vector elements.

The named predicate constraint limits the number of active elements in a single predicate to:

- A fixed number (VL1 to VL256)
- The largest power of two (POW2)
- The largest multiple of three or four (MUL3 or MUL4)
- All available, implicitly a multiple of two (ALL).

Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.

It has encodings from 3 classes: Doubleword , Halfword and Word

### Doubleword

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | imm4 | 1 | 1 | 0 | 0 | 0 | 1 | pattern | Zdn
| size<1> | size<0> |  |  |  | D |  |

####

DECD <Zdn>.D{, <pattern>{, MUL #<imm>}}

if !HaveSVE() && !HaveSME() then UNDEFINED; constant integer esize = 64; integer dn = UInt(Zdn); bits(5) pat = pattern; integer imm = UInt(imm4) + 1;

### Halfword

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | imm4 | 1 | 1 | 0 | 0 | 0 | 1 | pattern | Zdn
| size<1> | size<0> |  |  |  | D |  |

####

DECH <Zdn>.H{, <pattern>{, MUL #<imm>}}

if !HaveSVE() && !HaveSME() then UNDEFINED; constant integer esize = 16; integer dn = UInt(Zdn); bits(5) pat = pattern; integer imm = UInt(imm4) + 1;

### Word

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | imm4 | 1 | 1 | 0 | 0 | 0 | 1 | pattern | Zdn
| size<1> | size<0> |  |  |  | D |  |

####

DECW <Zdn>.S{, <pattern>{, MUL #<imm>}}

if !HaveSVE() && !HaveSME() then UNDEFINED; constant integer esize = 32; integer dn = UInt(Zdn); bits(5) pat = pattern; integer imm = UInt(imm4) + 1;

### Assembler Symbols

<Zdn> | Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

<pattern> | Is the optional pattern specifier, defaulting to ALL, encoded in pattern:
pattern | <pattern>
--- | ---
00000 | POW2
00001 | VL1
00010 | VL2
00011 | VL3
00100 | VL4
00101 | VL5
00110 | VL6
00111 | VL7
01000 | VL8
01001 | VL16
01010 | VL32
01011 | VL64
01100 | VL128
01101 | VL256
0111x | #uimm5
101x1 | #uimm5
10110 | #uimm5
1x0x1 | #uimm5
1x010 | #uimm5
1xx00 | #uimm5
11101 | MUL4
11110 | MUL3
11111 | ALL

<imm> | Is the immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; integer count = DecodePredCount(pat, esize); bits(VL) operand1 = Z[dn, VL]; bits(VL) result; for e = 0 to elements-1 Elem[result, e, esize] = Elem[operand1, e, esize] - (count * imm); Z[dn, VL] = result;

### Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:

- The MOVPRFX instruction must be unpredicated.
- The MOVPRFX instruction must specify the same destination register as this instruction.
- The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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