Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## PRFD (scalar plus scalar)

Contiguous prefetch doublewords (scalar index)

Contiguous prefetch of doubleword elements from the memory address generated by a 64-bit scalar base and scalar index which is multiplied by 8 and added to the base address. After each element prefetch the index value is incremented, but the index register is not updated.

The predicate may be used to suppress prefetches from unwanted addresses.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | Rm | 1 | 1 | 0 | Pg | Rn | 0 | prfop
| msz<1> | msz<0> |  |  |  |  |  |  |

####

PRFD <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #3]

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; if Rm == '11111' then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer level = UInt(prfop<2:1>); constant boolean stream = (prfop<0> == '1'); constant PrefetchHint pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE; constant integer scale = 3;

### Assembler Symbols

<prfop> | Is the prefetch operation specifier, encoded in prfop:
prfop | <prfop>
--- | ---
0000 | PLDL1KEEP
0001 | PLDL1STRM
0010 | PLDL2KEEP
0011 | PLDL2STRM
0100 | PLDL3KEEP
0101 | PLDL3STRM
x11x | #uimm4
1000 | PSTL1KEEP
1001 | PSTL1STRM
1010 | PSTL2KEEP
1011 | PSTL2STRM
1100 | PSTL3KEEP
1101 | PSTL3STRM

<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xm> | Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field.

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; bits(64) base; bits(64) offset; if AnyActiveElement(mask, esize) then base = if n == 31 then SP[] else X[n, 64]; offset = X[m, 64]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant integer eoff = UInt(offset) + e; constant bits(64) addr = base + (eoff << scale); Hint_Prefetch(addr, pref_hint, level, stream);

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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