Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## FCMLA (by element)

Floating-point Complex Multiply Accumulate (by element).

This instruction operates on complex numbers that are represented in SIMD&FP registers as pairs of elements, with the more significant element holding the imaginary part of the number and the less significant element holding the real part of the number. Each element holds a floating-point value. It performs the following computation on complex numbers from the first source register and the destination register with the specified complex number from the second source register:

- Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees.
- The two elements of the transformed complex number are multiplied by:
  - The real element of the complex number from the first source register, if the transformation was a rotation by 0 or 180 degrees.
  - The imaginary element of the complex number from the first source register, if the transformation was a rotation by 90 or 270 degrees.
- The complex number resulting from that multiplication is added to the complex number from the destination register.

The multiplication and addition operations are performed as a fused multiply-add, without any intermediate rounding.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

### Vector
(FEAT_FCMA)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | size | L | M | Rm | 0 | rot | 1 | H | 0 | Rn | Rd

#### (size == 01)

FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>], #<rotate>

#### (size == 10)

FCMLA <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>], #<rotate>

if !HaveFCADDExt() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(M:Rm); integer index; if size == '00' || size == '11' then UNDEFINED; if size == '01' then index = UInt(H:L); if size == '10' then index = UInt(H); integer esize = 8 << UInt(size); if !HaveFP16Ext() && esize == 16 then UNDEFINED; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; if size == '10' && (L == '1' || Q == '0') then UNDEFINED; if size == '01' && H == '1' && Q == '0' then UNDEFINED;

### Assembler Symbols

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> | Is an arrangement specifier, encoded in size:Q:
size | Q | <T>
--- | --- | ---
00 | x | RESERVED
01 | 0 | 4H
01 | 1 | 8H
10 | 0 | RESERVED
10 | 1 | 4S
11 | x | RESERVED

<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm> | Is the name of the second SIMD&FP source register, encoded in the "M:Rm" fields.

<Ts> | Is an element size specifier, encoded in size:
size | <Ts>
--- | ---
00 | RESERVED
01 | H
10 | S
11 | RESERVED

<index> | Is the element index, encoded in size:H:L:
size | <index>
--- | ---
00 | RESERVED
01 | H:L
10 | H
11 | RESERVED

<rotate> | Is the rotation, encoded in rot:
rot | <rotate>
--- | ---
00 | 0
01 | 90
10 | 180
11 | 270

### Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n, datasize]; bits(datasize) operand2 = V[m, datasize]; bits(datasize) operand3 = V[d, datasize]; bits(datasize) result; FPCRType fpcr = FPCR[]; for e = 0 to (elements DIV 2)-1 bits(esize) element1; bits(esize) element2; bits(esize) element3; bits(esize) element4; case rot of when '00' element1 = Elem[operand2, index*2, esize]; element2 = Elem[operand1, e*2, esize]; element3 = Elem[operand2, index*2+1, esize]; element4 = Elem[operand1, e*2, esize]; when '01' element1 = FPNeg(Elem[operand2, index*2+1, esize]); element2 = Elem[operand1, e*2+1, esize]; element3 = Elem[operand2, index*2, esize]; element4 = Elem[operand1, e*2+1, esize]; when '10' element1 = FPNeg(Elem[operand2, index*2, esize]); element2 = Elem[operand1, e*2, esize]; element3 = FPNeg(Elem[operand2, index*2+1, esize]); element4 = Elem[operand1, e*2, esize]; when '11' element1 = Elem[operand2, index*2+1, esize]; element2 = Elem[operand1, e*2+1, esize]; element3 = FPNeg(Elem[operand2, index*2, esize]); element4 = Elem[operand1, e*2+1, esize]; Elem[result, e*2, esize] = FPMulAdd(Elem[operand3, e*2, esize], element2, element1, fpcr); Elem[result, e*2+1, esize] = FPMulAdd(Elem[operand3, e*2+1, esize], element4, element3, fpcr); V[d, datasize] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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