Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## LUTI2

Lookup table read with 2-bit indices. This instruction copies indexed 8-bit or 16-bit elements from the table vector to the destination vector using packed 2-bit indices from a segment of the source vector. A segment corresponds to a portion of the source vector that is consumed in order to fill the destination vector. The segment is selected by the vector segment index.

### Advanced SIMD
(FEAT_LUT)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | x | 0 | Rm | 0 | len | op | 0 | 0 | Rn | Rd
|  |  | op2 |  |  |  |  |  |  |  |

#### Byte (op2 == 10 && op == 1)

LUTI2 <Vd>.16B, { <Vn>.16B }, <Vm>[<index>]

#### Halfword (op2 == 11)

LUTI2 <Vd>.8H, { <Vn>.8H }, <Vm>[<index>]

if !IsFeatureImplemented(FEAT_LUT) then UNDEFINED; if op2 == '10' && op == '0' then UNDEFINED; integer isize = 2; integer esize = if op2 == '10' then 8 else 16; integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); integer part = if op2 == '10' then UInt(len) else UInt(len:op);

### Assembler Symbols

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn> | Is the name of the SIMD&FP table register, encoded in the "Rn" field.

<Vm> | Is the name of the SIMD&FP source register, encoded in the "Rm" field.

<index> | For the byte variant: is the vector segment index, in the range 0 to 3, encoded in the "len" field.
| For the halfword variant: is the vector segment index, in the range 0 to 7, encoded in the "len:op" fields.

### Operation

CheckFPAdvSIMDEnabled64(); integer elements = 128 DIV esize; integer ibase = elements * part; bits(128) indices = V[m, 128]; bits(128) table = V[n, 128]; bits(128) result; for e = 0 to elements-1 integer index = UInt(Elem[indices, ibase+e, isize]); Elem[result, e, esize] = Elem[table, index, esize]; V[d, 128] = result;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.