Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## FAMAX

Floating-point absolute maximum. This instruction determines the maximum absolute value from floating-point elements of the first source vector and the corresponding floating-point elements of the second source vector, and places the results in the corresponding elements of the destination vector.

The behavior is as follows:

- When FPCR.DN is 0, if either element is a NaN, the result is a quiet NaN.
- When FPCR.DN is 1, if either element is a NaN, the result is the Default NaN.
- Denormalized inputs and results are never flushed to zero, as if FPCR.{FZ, FZ16, FIZ} is {0, 0, 0}.
- Denormalized inputs never generate an Input Denormal floating-point exception.

It has encodings from 2 classes: Half-precision and Single-precision and double-precision

### Half-precision
(FEAT_FAMINMAX)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | Rm | 0 | 0 | 0 | 1 | 1 | 1 | Rn | Rd
|  | U |  | a |  |  |  | opcode |  |  |

####

FAMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

if !IsFeatureImplemented(FEAT_FAMINMAX) then UNDEFINED; constant integer esize = 16; integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); constant integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean ismax = U == '0';

### Single-precision and double-precision
(FEAT_FAMINMAX)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 1 | x | 1 | Rm | 1 | 1 | 0 | 1 | 1 | 1 | Rn | Rd
|  | U |  | size |  |  | opcode |  |  |

####

FAMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

if !IsFeatureImplemented(FEAT_FAMINMAX) then UNDEFINED; if Q == '0' && size == '11' then UNDEFINED; constant integer esize = 8 << UInt(size); integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); constant integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize; boolean ismax = U == '0';

### Assembler Symbols

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> | For the half-precision variant: is an arrangement specifier, encoded in Q:
Q | <T>
--- | ---
0 | 4H
1 | 8H
| For the single-precision and double-precision variant: is an arrangement specifier, encoded in size<0>:Q:
size<0> | Q | <T>
--- | --- | ---
0 | 0 | 2S
0 | 1 | 4S
1 | 0 | RESERVED
1 | 1 | 2D

<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm> | Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

### Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n, datasize]; bits(datasize) operand2 = V[m, datasize]; bits(datasize) result; for e = 0 to elements-1 bits(esize) op1 = Elem[operand1, e, esize]; bits(esize) op2 = Elem[operand2, e, esize]; if ismax then Elem[result, e, esize] = FPAbsMax(op1, op2, FPCR); else Elem[result, e, esize] = FPAbsMin(op1, op2, FPCR); V[d, datasize] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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