Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## SLI

Shift left and insert (immediate)

Shift each source vector element left by an immediate value, and insert the result into the corresponding vector element in the destination vector register, merging the shifted bits from each source element with existing bits in each destination vector element. The immediate shift amount is an unsigned value in the range 0 to number of bits per element minus 1. This instruction is unpredicated.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | tszh | 0 | tszl | imm3 | 1 | 1 | 1 | 1 | 0 | 1 | Zn | Zd

####

SLI <Zd>.<T>, <Zn>.<T>, #<const>

if !HaveSVE2() && !HaveSME() then UNDEFINED; bits(4) tsize = tszh:tszl; integer esize; case tsize of when '0000' UNDEFINED; when '0001' esize = 8; when '001x' esize = 16; when '01xx' esize = 32; when '1xxx' esize = 64; integer n = UInt(Zn); integer d = UInt(Zd); constant integer shift = UInt(tsize:imm3) - esize;

### Assembler Symbols

<Zd> | Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> | Is the size specifier, encoded in tszh:tszl:
tszh | tszl | <T>
--- | --- | ---
00 | 00 | RESERVED
00 | 01 | B
00 | 1x | H
01 | xx | S
1x | xx | D

<Zn> | Is the name of the first source scalable vector register, encoded in the "Zn" field.

<const> | Is the immediate shift amount, in the range 0 to number of bits per element minus 1, encoded in "tsz:imm3".

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(VL) operand = Z[n, VL]; bits(VL) result = Z[d, VL]; for e = 0 to elements-1 bits(esize) element1 = Elem[result, e, esize]; bits(esize) element2 = Elem[operand, e, esize]; bits(esize) mask = LSL(Ones(esize), shift); bits(esize) shiftedval = LSL(element2, shift); Elem[result, e, esize] = (element1 AND (NOT mask)) OR shiftedval; Z[d, VL] = result;

### Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then when PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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