Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element)

8-bit floating-point multiply-add long-long to single-precision (vector, by element). This instruction widens the first (bottom bottom), second (bottom top), third (top bottom), or fourth (top top) 8-bit element of each 32-bit container in the first source vector and the indexed element from the second source vector to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE), before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the first source vector.

The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.

### Advanced SIMD
(FEAT_FP8FMA)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | 0 | x | L | M | Rm | 1 | 0 | 0 | 0 | H | 0 | Rn | Rd
|  |  |  | size |  |  |  |  |  |  |  |

#### FMLALLBB (Q == 0 && size == 00)

FMLALLBB <Vd>.4S, <Vn>.16B, <Vm>.B[<index>]

#### FMLALLBT (Q == 0 && size == 01)

FMLALLBT <Vd>.4S, <Vn>.16B, <Vm>.B[<index>]

#### FMLALLTB (Q == 1 && size == 00)

FMLALLTB <Vd>.4S, <Vn>.16B, <Vm>.B[<index>]

#### FMLALLTT (Q == 1 && size == 01)

FMLALLTT <Vd>.4S, <Vn>.16B, <Vm>.B[<index>]

if !IsFeatureImplemented(FEAT_FP8FMA) then UNDEFINED; integer n = UInt(Rn); integer m = UInt('00':Rm<2:0>); integer d = UInt(Rd); integer index = UInt(H:L:M:Rm<3>); constant integer elements = 128 DIV 32; integer sel = UInt(Q:size<0>);

### Assembler Symbols

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm> | Is the name of the second SIMD&FP source register, in the range V0 to V7, encoded in the "Rm<2:0>" field.

<index> | Is the element index, in the range 0 to 15, encoded in the "H:L:M:Rm<3>" fields.

### Operation

CheckFPMREnabled(); CheckFPAdvSIMDEnabled64(); bits(128) operand1 = V[n, 128]; bits(128) operand2 = V[m, 128]; bits(128) operand3 = V[d, 128]; bits(128) result; for e = 0 to elements-1 bits(8) element1 = Elem[operand1, 4*e+sel, 8]; bits(8) element2 = Elem[operand2, index, 8]; bits(32) element3 = Elem[operand3, e, 32]; Elem[result, e, 32] = FP8MulAddFP(element3, element1, element2, FPCR, FPMR); V[d, 128] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.