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# GICD_TYPER2, Interrupt Controller Type Register 2

The GICD_TYPER2 characteristics are:

## Purpose

Provides information about which features the GIC implementation supports.

## Configuration

This register is present only when GICv4.1 is implemented. Otherwise, direct accesses to GICD_TYPER2 are RES0.

When GICD_CTLR.DS == 0, this register is Common.

## Attributes

GICD_TYPER2 is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | nASSGIcap | VIL | RES0 | VID

#### Bits [31:9]

Reserved, RES0.

#### nASSGIcap, bit [8]

Indicates whether SGIs can be configured to not have an active state.

The value of this field is an IMPLEMENTATION DEFINED choice of:

nASSGIcap | Meaning
--- | ---
0b0 | SGIs have an active state.
0b1 | SGIs can be globally configured not to have an active state.

This bit is RES0 on implementations that support two Security states.

Access to this field is RO.

#### VIL, bit [7]

Indicates whether 16 bits of vPEID are implemented.

The value of this field is an IMPLEMENTATION DEFINED choice of:

VIL | Meaning
--- | ---
0b0 | GIC supports 16-bit vPEID.
0b1 | GIC supports GICD_TYPER2.VID + 1 bits of vPEID.

Access to this field is RO.

#### Bits [6:5]

Reserved, RES0.

#### VID, bits [4:0]

When GICD_TYPER2.VIL == 1, the number of bits is equal to the bits of vPEID minus one.

When GICD_TYPER2.VIL == 0, this field is RES0.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

## Accessing GICD_TYPER2

#### GICD_TYPER2 can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
GIC Distributor | Dist_base | 0x000C | GICD_TYPER2

Accesses on this interface are RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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