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# CNTP_CVAL, Counter-timer Physical Timer CompareValue register

The CNTP_CVAL characteristics are:

## Purpose

Holds the compare value for the EL1 physical timer.

## Configuration

This register is banked between CNTP_CVAL and CNTP_CVAL_S and CNTP_CVAL_NS.

AArch32 System register CNTP_CVAL bits [63:0] are architecturally mapped to AArch64 System register CNTP_CVAL_EL0[63:0].

This register is present only when AArch32 is supported. Otherwise, direct accesses to CNTP_CVAL are UNDEFINED.

## Attributes

CNTP_CVAL is a 64-bit register.

This register has the following instances:

- CNTP_CVAL, when EL3 is not implemented.
- CNTP_CVAL_S, when EL3 is implemented.
- CNTP_CVAL_NS, when EL3 is implemented.

## Field descriptions

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CompareValue
CompareValue

#### CompareValue, bits [63:0]

Holds the EL1 physical timer CompareValue.

When CNTP_CTL.ENABLE is 1, the timer condition is met when (CNTPCT - CompareValue) is greater than or equal to zero. This means that CompareValue acts like a 64-bit upcounter timer. When the timer condition is met:

- CNTP_CTL.ISTATUS is set to 1.
- If CNTP_CTL.IMASK is 0, an interrupt is generated.

When CNTP_CTL.ENABLE is 0, the timer condition is not met, but CNTPCT continues to count.

If the Generic counter is implemented at a size less than 64 bits, then this field is permitted to be implemented at the same width as the counter, and the upper bits are RES0.

The value of this field is treated as zero-extended in all counter calculations.

The reset behavior of this field is:

- On a Warm reset, this field resets to an architecturally UNKNOWN value.

## Accessing CNTP_CVAL

Accesses to this register use the following encodings in the System register encoding space:

#### MRRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>

coproc | CRm | opc1
--- | --- | ---
0b1111 | 0b1110 | 0b0010

if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CNTKCTL_EL1.EL0PTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); else AArch64.AArch32SystemAccessTrap(EL1, 0x04); elsif ELUsingAArch32(EL1) && CNTKCTL.PL0PTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif ELIsInHost(EL2) && HCR_EL2.TGE == '0' && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && CNTHCTL.PL1PCEN == '0' then AArch32.TakeHypTrapException(0x04); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then (R[t2], R[t]) = (CNTHPS_CVAL_EL2<63:32>, CNTHPS_CVAL_EL2<31:0>); elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then (R[t2], R[t]) = (CNTHP_CVAL_EL2<63:32>, CNTHP_CVAL_EL2<31:0>); else (R[t2], R[t]) = (CNTP_CVAL<63:32>, CNTP_CVAL<31:0>); elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif ELIsInHost(EL2) && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && CNTHCTL.PL1PCEN == '0' then AArch32.TakeHypTrapException(0x04); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then (R[t2], R[t]) = (CNTP_CVAL_NS<63:32>, CNTP_CVAL_NS<31:0>); else (R[t2], R[t]) = (CNTP_CVAL<63:32>, CNTP_CVAL<31:0>); elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then (R[t2], R[t]) = (CNTP_CVAL_NS<63:32>, CNTP_CVAL_NS<31:0>); else (R[t2], R[t]) = (CNTP_CVAL<63:32>, CNTP_CVAL<31:0>); elsif PSTATE.EL == EL3 then if SCR.NS == '0' then (R[t2], R[t]) = (CNTP_CVAL_S<63:32>, CNTP_CVAL_S<31:0>); else (R[t2], R[t]) = (CNTP_CVAL_NS<63:32>, CNTP_CVAL_NS<31:0>);

#### MCRR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>

coproc | CRm | opc1
--- | --- | ---
0b1111 | 0b1110 | 0b0010

if PSTATE.EL == EL0 then if !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && CNTKCTL_EL1.EL0PTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); else AArch64.AArch32SystemAccessTrap(EL1, 0x04); elsif ELUsingAArch32(EL1) && CNTKCTL.PL0PTEN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif ELIsInHost(EL2) && HCR_EL2.TGE == '0' && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif ELIsInHost(EL0) && CNTHCTL_EL2.EL0PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && CNTHCTL.PL1PCEN == '0' then AArch32.TakeHypTrapException(0x04); elsif ELIsInHost(EL0) && IsCurrentSecurityState(SS_Secure) && IsFeatureImplemented(FEAT_SEL2) then CNTHPS_CVAL_EL2 = R[t2]:R[t]; elsif ELIsInHost(EL0) && !IsCurrentSecurityState(SS_Secure) then CNTHP_CVAL_EL2 = R[t2]:R[t]; else CNTP_CVAL = R[t2]:R[t]; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && !ELIsInHost(EL2) && CNTHCTL_EL2.EL1PCEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif ELIsInHost(EL2) && CNTHCTL_EL2.EL1PTEN == '0' then AArch64.AArch32SystemAccessTrap(EL2, 0x04); elsif EL2Enabled() && ELUsingAArch32(EL2) && CNTHCTL.PL1PCEN == '0' then AArch32.TakeHypTrapException(0x04); elsif HaveEL(EL3) && ELUsingAArch32(EL3) then CNTP_CVAL_NS = R[t2]:R[t]; else CNTP_CVAL = R[t2]:R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && ELUsingAArch32(EL3) then CNTP_CVAL_NS = R[t2]:R[t]; else CNTP_CVAL = R[t2]:R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then CNTP_CVAL_S = R[t2]:R[t]; else CNTP_CVAL_NS = R[t2]:R[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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