Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## LDG

Load Allocation Tag loads an Allocation Tag from a memory address, generates a Logical Address Tag from the Allocation Tag and merges it into the destination register. The address used for the load is calculated from the base register and an immediate signed offset scaled by the Tag granule.

### Integer
(FEAT_MTE)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | imm9 | 0 | 0 | Xn | Xt

####

LDG <Xt>, [<Xn|SP>{, #<simm>}]

if !IsFeatureImplemented(FEAT_MTE) then UNDEFINED; integer t = UInt(Xt); integer n = UInt(Xn); bits(64) offset = LSL(SignExtend(imm9, 64), LOG2_TAG_GRANULE);

### Assembler Symbols

<Xt> | Is the 64-bit name of the general-purpose destination register, encoded in the "Xt" field.

<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field.

<simm> | Is the optional signed immediate offset, a multiple of 16 in the range -4096 to 4080, defaulting to 0 and encoded in the "imm9" field.

### Operation

bits(64) address; bits(4) tag; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; AccessDescriptor accdesc = CreateAccDescLDGSTG(MemOp_LOAD); address = GenerateAddress(address, offset, accdesc); address = Align(address, TAG_GRANULE); tag = AArch64.MemTag[address, accdesc]; X[t, 64] = AArch64.AddressWithAllocationTag(X[t, 64], tag);

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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