Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## WHILEWR

While free of write-after-read/write conflicts

This instruction checks two addresses for a conflict or overlap between address ranges of the form [addr,addr+VL÷8), where VL is the accessible vector length in bits, that could result in a loop-carried dependency through memory due to the use of these addresses by contiguous load and store instructions within the same iteration of a loop. Generate a predicate whose elements are true while the addresses cannot conflict within the same iteration, and false thereafter. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | size | 1 | Rm | 0 | 0 | 1 | 1 | 0 | 0 | Rn | 0 | Pd
|  |  |  |  |  | rw |

####

WHILEWR <Pd>.<T>, <Xn>, <Xm>

if !HaveSVE2() && !HaveSME() then UNDEFINED; constant integer esize = 8 << UInt(size); integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Pd);

### Assembler Symbols

<Pd> | Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<T> | Is the size specifier, encoded in size:
size | <T>
--- | ---
00 | B
01 | H
10 | S
11 | D

<Xn> | Is the 64-bit name of the first source general-purpose register, encoded in the "Rn" field.

<Xm> | Is the 64-bit name of the second source general-purpose register, encoded in the "Rm" field.

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(PL) mask = Ones(PL); bits(64) src1 = X[n, 64]; bits(64) src2 = X[m, 64]; integer operand1 = UInt(src1); integer operand2 = UInt(src2); bits(PL) result; constant integer psize = esize DIV 8; integer diff = (operand2 - operand1) DIV (esize DIV 8); for e = 0 to elements-1 if diff <= 0 || e < diff then Elem[result, e, psize] = ZeroExtend('1', psize); else Elem[result, e, psize] = ZeroExtend('0', psize); PSTATE.<N,Z,C,V> = PredTest(mask, result, esize); P[d, PL] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.