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# MIDR_EL1, Main ID Register

The MIDR_EL1 characteristics are:

## Purpose

Provides identification information for the PE, including an implementer code for the device and a device ID number.

## Configuration

External register MIDR_EL1 bits [31:0] are architecturally mapped to AArch64 System register MIDR_EL1[31:0].

External register MIDR_EL1 bits [31:0] are architecturally mapped to AArch32 System register MIDR[31:0].

The power domain of MIDR_EL1 is IMPLEMENTATION DEFINED.

## Attributes

MIDR_EL1 is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Implementer | Variant | Architecture | PartNum | Revision

#### Implementer, bits [31:24]

The Implementer code. This field must hold an implementer code that has been assigned by Arm.

The value of this field is an IMPLEMENTATION DEFINED choice of:

Implementer | Meaning
--- | ---
0x00 | Reserved for software use.
0x41 | Arm Limited.
0x42 | Broadcom Corporation.
0x43 | Cavium Inc.
0x44 | Digital Equipment Corporation.
0x46 | Fujitsu Ltd.
0x49 | Infineon Technologies AG.
0x4D | Motorola or Freescale Semiconductor Inc.
0x4E | NVIDIA Corporation.
0x50 | Applied Micro Circuits Corporation.
0x51 | Qualcomm Inc.
0x56 | Marvell International Ltd.
0x69 | Intel Corporation.
0xC0 | Ampere Computing.

Arm can assign codes that are not published in this manual. All values not assigned by Arm are reserved and must not be used.

Access to this field is RO.

#### Variant, bits [23:20]

Variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### Architecture, bits [19:16]

Architecture version.

The value of this field is an IMPLEMENTATION DEFINED choice of:

Architecture | Meaning
--- | ---
0b0001 | Armv4.
0b0010 | Armv4T.
0b0011 | Armv5 (obsolete).
0b0100 | Armv5T.
0b0101 | Armv5TE.
0b0110 | Armv5TEJ.
0b0111 | Armv6.
0b1111 | Architectural features are individually identified in the ID_* registers.

All other values are reserved.

Access to this field is RO.

#### PartNum, bits [15:4]

Primary Part Number for the device.

On processors implemented by Arm, if the top four bits of the primary part number are 0x0 or 0x7, the variant and architecture are encoded differently.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### Revision, bits [3:0]

Revision number for the device.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

## Accessing MIDR_EL1

#### MIDR_EL1 can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
Debug | 0xD00 | MIDR_EL1

This interface is accessible as follows:

- When DoubleLockStatus() or !IsCorePowered(), accesses to this register are IMPDEF.
- Otherwise, accesses to this register are RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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