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## DUPQ

Broadcast indexed element within each quadword vector segment (unpredicated)

Unconditionally broadcast the indexed element within each 128-bit source vector segment to all elements of the corresponding destination vector segment. This instruction is unpredicated.

The immediate element index is in the range of 0 to 15 (bytes), 7 (halfwords), 3 (words) or 1 (doublewords).

### SVE2
(FEAT_SVE2p1)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | i1 | tsz | 0 | 0 | 1 | 0 | 0 | 1 | Zn | Zd

####

DUPQ <Zd>.<T>, <Zn>.<T>[<imm>]

if !HaveSVE2p1() && !HaveSME2p1() then UNDEFINED; bits(5) imm = i1:tsz; integer esize; integer index; case tsz of when '0000' UNDEFINED; when '1000' esize = 64; index = UInt(imm<4:4>); when 'x100' esize = 32; index = UInt(imm<4:3>); when 'xx10' esize = 16; index = UInt(imm<4:2>); when 'xxx1' esize = 8; index = UInt(imm<4:1>); integer n = UInt(Zn); integer d = UInt(Zd);

### Assembler Symbols

<Zd> | Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> | Is the size specifier, encoded in tsz:
tsz | <T>
--- | ---
0000 | RESERVED
xxx1 | B
xx10 | H
x100 | S
1000 | D

<Zn> | Is the name of the source scalable vector register, encoded in the "Zn" field.

<imm> | Is the immediate index, in the range 0 to one less than the number of elements in 128 bits, encoded in "i1:tsz".

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer segments = VL DIV 128; constant integer elements = 128 DIV esize; bits(VL) operand = Z[n, VL]; bits(VL) result; bits(esize) element; for s = 0 to segments-1 element = Elem[operand, s * elements + index, esize]; Elem[result, s, 128] = Replicate(element, 128 DIV esize); Z[d, VL] = result;

### Operational information

When PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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