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# HCPTR, Hyp Architectural Feature Trap Register

The HCPTR characteristics are:

## Purpose

Controls:

- Trapping to Hyp mode of Non-secure access, at EL1 or EL0, to trace, and to Advanced SIMD and floating-point functionality.
- Hyp mode access to trace, and to Advanced SIMD and floating-point functionality.

Note

Accesses to this functionality:

- From Non-secure modes other than Hyp mode are also affected by settings in the CPACR and NSACR.
- From Hyp mode are also affected by settings in the NSACR.

Exceptions generated by the CPACR and NSACR controls are higher priority than those generated by the HCPTR controls.

## Configuration

AArch32 System register HCPTR bits [31:0] are architecturally mapped to AArch64 System register CPTR_EL2[31:0].

This register is present only when EL2 is capable of using AArch32. Otherwise, direct accesses to HCPTR are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

## Attributes

HCPTR is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TCPAC | TAM | RES0 | TTA | RES0 | TASE | RES0 | RES1 | TCP11 | TCP10 | RES1

#### TCPAC, bit [31]

Traps Non-secure EL1 MRC and MCR accesses to the CPACR to Hyp mode, reported using EC syndrome value 0x03.

TCPAC | Meaning
--- | ---
0b0 | This control does not cause any instructions to be trapped.
0b1 | Non-secure EL1 accesses to the CPACR are trapped to Hyp mode.

Note

The CPACR is not accessible at EL0.

The reset behavior of this field is:

- On a Warm reset:
  - When the highest implemented Exception level is EL3 or the highest implemented Exception level is EL2, this field resets to 0.
  - Otherwise, this field resets to an architecturally UNKNOWN value.

#### TAM, bit [30]
When FEAT_AMUv1 is implemented:

Trap Activity Monitor access. Traps Non-secure EL1 and EL0 MRC, MCR, MRRC, and MCRR accesses to all Activity Monitor registers to EL2, reported using EC syndrome values 0x03 and 0x04.

TAM | Meaning
--- | ---
0b0 | This control does not cause any instructions to be trapped.
0b1 | Accesses from Non-secure EL1 and EL0 to Activity Monitor registers are trapped to Hyp mode.

The reset behavior of this field is:

- On a Warm reset:
  - When the highest implemented Exception level is EL3 or the highest implemented Exception level is EL2, this field resets to 0.
  - Otherwise, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bits [29:21]

Reserved, RES0.

#### TTA, bit [20]

Traps Non-secure System register MRC, MCR, MRRC, and MCRR accesses to all implemented trace registers to Hyp mode, reported using EC syndrome values 0x05 and 0x0C.

TTA | Meaning
--- | ---
0b0 | This control does not cause any instructions to be trapped.
0b1 | Any Non-secure System register access to an implemented trace register is trapped to Hyp mode, unless the access is trapped to EL1 by a CPACR or NSACR control, or the access is from Non-secure EL0 and the definition of the register in the appropriate trace architecture specification indicates that the register is not accessible from EL0. A trapped instruction generates: A Hyp Trap exception, if the exception is taken from Non-secure EL0 or EL1. An Undefined Instruction exception taken to Hyp mode, if the exception is taken from Hyp mode.

If the implementation does not include a trace unit, or does not include a System register interface to the trace unit registers, it is IMPLEMENTATION DEFINED whether this bit:

- Is RES0.
- Is RES1.
- Can be written from Hyp mode, and from Secure Monitor mode when SCR.NS is 1.

If EL3 is implemented and is using AArch32, and the value of NSACR.NSTRCDIS is 1, in Non-secure state this field behaves as RAO/WI, regardless of its actual value.

Note

- The ETMv4 architecture and ETE do not permit EL0 to access the trace registers. If the trace unit implements FEAT_ETMv4 or FEAT_ETE, EL0 accesses to the trace registers are UNDEFINED, and a resulting Undefined Instruction exception is higher priority than a HCPTR.TTA Hyp Trap exception.
- The Arm architecture does not provide traps on trace register accesses through the optional memory-mapped debug interface.

System register accesses to the trace registers can have side-effects. When a System register access is trapped, any side-effects that are normally associated with the access do not occur before the exception is taken.

The reset behavior of this field is:

- On a Warm reset:
  - When the highest implemented Exception level is EL3 or the highest implemented Exception level is EL2, this field resets to 0.
  - Otherwise, this field resets to an architecturally UNKNOWN value.

#### Bits [19:16]

Reserved, RES0.

#### TASE, bit [15]

Traps Non-secure execution of Advanced SIMD instructions to Hyp mode, reported using EC syndrome value 0x07, when the value of HCPTR.TCP10 is 0.

TASE | Meaning
--- | ---
0b0 | This control does not cause any instructions to be trapped.
0b1 | When the value of HCPTR.TCP10 is 0, any attempt to execute an Advanced SIMD instruction in Non-secure state is trapped to Hyp mode, unless it is trapped to EL1 by a CPACR or NSACR control. A trapped instruction generates: A Hyp Trap exception, if the exception is taken from Non-secure EL0 or EL1. An Undefined Instruction exception taken to Hyp mode, if the exception is taken from Hyp mode.

When the value of HCPTR.TCP10 is 1, the value of this field is ignored.

If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES1. Otherwise, it is IMPLEMENTATION DEFINED whether this field is implemented as a RW field. If it is not implemented as a RW field, then it is RAZ/WI.

If EL3 is implemented and is using AArch32, and the value of NSACR.NSASEDIS is 1, in Non-secure state this field behaves as RAO/WI, regardless of its actual value. This applies even if the field is implemented as RAZ/WI.

For the list of instructions affected by this field, see 'Controls of Advanced SIMD operation that do not apply to floating-point operation'.

The reset behavior of this field is:

- On a Warm reset:
  - When the highest implemented Exception level is EL3 or the highest implemented Exception level is EL2, this field resets to 0.
  - Otherwise, this field resets to an architecturally UNKNOWN value.

#### Bit [14]

Reserved, RES0.

#### Bits [13:12]

Reserved, RES1.

#### TCP11, bit [11]
When FEAT_FP is implemented and FEAT_AdvSIMD is implemented:

The value of this field is ignored. If this field is programmed with a different value to the TCP10 bit then this field is UNKNOWN on a direct read of the HCPTR.

If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES1.

If EL3 is implemented and is using AArch32, and the value of NSACR.cp10 is 0, in Non-secure state this field behaves as RAO/WI, regardless of its actual value.

The reset behavior of this field is:

- On a Warm reset:
  - When the highest implemented Exception level is EL3 or the highest implemented Exception level is EL2, this field resets to 0.
  - Otherwise, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

- Access is RAO/WI if EL3 is implemented and EL3 is using AArch32 and !IsCurrentSecurityState(SS_Secure) and NSACR.cp10 == 0.

####
Otherwise:

Reserved, RES1.

#### TCP10, bit [10]
When FEAT_FP is implemented and FEAT_AdvSIMD is implemented:

Trap Non-secure accesses to Advanced SIMD and floating-point functionality to Hyp mode, reported using EC syndrome value 0x07:

TCP10 | Meaning
--- | ---
0b0 | This control does not cause any instructions to be trapped.
0b1 | Any attempted access to Advanced SIMD and floating-point functionality from Non-secure state is trapped to Hyp mode, unless it is trapped to EL1 by a CPACR or NSACR control. A trapped instruction generates: A Hyp Trap exception, if the exception is taken from Non-secure EL0 or EL1. An Undefined Instruction exception taken to Hyp mode, if the exception is taken from Hyp mode.

The Advanced SIMD and floating-point features controlled by these fields are:

- Execution of any floating-point or Advanced SIMD instruction.
- Any access to the Advanced SIMD and floating-point registers D0-D31 and their views as S0-S31 and Q0-Q15.
- Any access to the FPSCR, FPSID, MVFR0, MVFR1, MVFR2, or FPEXC System registers.

If the implementation does not include Advanced SIMD and floating-point functionality, this field is RES1.

If EL3 is implemented and is using AArch32, and the value of NSACR.cp10 is 0, in Non-secure state this field behaves as RAO/WI, regardless of its actual value.

The reset behavior of this field is:

- On a Warm reset:
  - When the highest implemented Exception level is EL3 or the highest implemented Exception level is EL2, this field resets to 0.
  - Otherwise, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

- Access is RAO/WI if EL3 is implemented and EL3 is using AArch32 and !IsCurrentSecurityState(SS_Secure) and NSACR.cp10 == 0.

####
Otherwise:

Reserved, RES1.

#### Bits [9:0]

Reserved, RES1.

## Accessing HCPTR

Accesses to this register use the following encodings in the System register encoding space:

#### MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b100 | 0b0001 | 0b0001 | 0b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && CPTR_EL3.TCPAC == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TCPAC == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else R[t] = HCPTR; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then UNDEFINED; else R[t] = HCPTR;

#### MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc | opc1 | CRn | CRm | opc2
--- | --- | --- | --- | ---
0b1111 | 0b100 | 0b0001 | 0b0001 | 0b010

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T1 == '1' then AArch32.TakeHypTrapException(0x03); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && CPTR_EL3.TCPAC == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && CPTR_EL3.TCPAC == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else HCPTR = R[t]; elsif PSTATE.EL == EL3 then if SCR.NS == '0' then UNDEFINED; else HCPTR = R[t];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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