Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## BSL1N

Bitwise select with first input inverted

Selects bits from the inverted first source vector where the corresponding bit in the third source vector is '1', and from the second source vector where the corresponding bit in the third source vector is '0'. The result is placed destructively in the destination and first source vector. This instruction is unpredicated.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | Zm | 0 | 0 | 1 | 1 | 1 | 1 | Zk | Zdn

####

BSL1N <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D

if !HaveSVE2() && !HaveSME() then UNDEFINED; integer m = UInt(Zm); integer k = UInt(Zk); integer dn = UInt(Zdn);

### Assembler Symbols

<Zdn> | Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.

<Zm> | Is the name of the second source scalable vector register, encoded in the "Zm" field.

<Zk> | Is the name of the third source scalable vector register, encoded in the "Zk" field.

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; bits(VL) operand1 = Z[dn, VL]; bits(VL) operand2 = Z[m, VL]; bits(VL) operand3 = Z[k, VL]; Z[dn, VL] = (NOT(operand1) AND operand3) OR (operand2 AND NOT(operand3));

### Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then when PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:

- The MOVPRFX instruction must be unpredicated.
- The MOVPRFX instruction must specify the same destination register as this instruction.
- The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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