AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# AMPIDR4, Activity Monitors Peripheral Identification Register 4

The AMPIDR4 characteristics are:

## Purpose

Provides information to identify an activity monitors component.

For more information, see 'About the Peripheral identification scheme'.

## Configuration

It is IMPLEMENTATION DEFINED whether AMPIDR4 is implemented in the Core power domain or in the Debug power domain.

This register is present only when FEAT_AMUv1 is implemented and an implementation implements AMPIDR4. Otherwise, direct accesses to AMPIDR4 are RES0.

## Attributes

AMPIDR4 is a 32-bit register.

This register is part of the AMU block.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | SIZE | DES_2

#### Bits [31:8]

Reserved, RES0.

#### SIZE, bits [7:4]

Size of the component. Log2 of the number of 4KB pages from the start of the component to the end of the component ID registers.

Reads as 0b0000.

Access to this field is RO.

#### DES_2, bits [3:0]

Designer. JEP106 continuation code, least significant nibble.

For Arm Limited, this field is 0b0100.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

## Accessing AMPIDR4

Accesses to this register use the following encodings:

Accessible at offset 0xFD0 from AMU

Accesses on this interface are RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.