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# ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0

The ID_MMFR0_EL1 characteristics are:

## Purpose

Provides information about the implemented memory model and memory management support in AArch32 state.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.

## Configuration

AArch64 System register ID_MMFR0_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_MMFR0[31:0].

## Attributes

ID_MMFR0_EL1 is a 64-bit register.

## Field descriptions

### When AArch32 is supported:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0
InnerShr | FCSE | AuxReg | TCM | ShareLvl | OuterShr | PMSA | VMSA

#### Bits [63:32]

Reserved, RES0.

#### InnerShr, bits [31:28]

Innermost Shareability. Indicates the innermost shareability domain implemented.

The value of this field is an IMPLEMENTATION DEFINED choice of:

InnerShr | Meaning
--- | ---
0b0000 | Implemented as Non-cacheable.
0b0001 | Implemented with hardware coherency support.
0b1111 | Shareability ignored.

All other values are reserved.

From Armv8 the permitted values are 0b0000, 0b0001, and 0b1111.

This field is valid only if the implementation supports two levels of shareability, as indicated by ID_MMFR0_EL1.ShareLvl having the value 0b0001.

When ID_MMFR0_EL1.ShareLvl is zero, this field is UNKNOWN.

Access to this field is RO.

#### FCSE, bits [27:24]

Indicates whether the implementation includes the FCSE.

The value of this field is an IMPLEMENTATION DEFINED choice of:

FCSE | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | Support for FCSE.

All other values are reserved.

From Armv8 the only permitted value is 0b0000.

Access to this field is RO.

#### AuxReg, bits [23:20]

Auxiliary Registers. Indicates support for Auxiliary registers.

The value of this field is an IMPLEMENTATION DEFINED choice of:

AuxReg | Meaning
--- | ---
0b0000 | None supported.
0b0001 | Support for Auxiliary Control Register only.
0b0010 | Support for Auxiliary Fault Status Registers (AIFSR and ADFSR) and Auxiliary Control Register.

All other values are reserved.

From Armv8 the only permitted value is 0b0010.

Note

Accesses to unimplemented Auxiliary registers are UNDEFINED.

Access to this field is RO.

#### TCM, bits [19:16]

Indicates support for TCMs and associated DMAs.

The value of this field is an IMPLEMENTATION DEFINED choice of:

TCM | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | Support is IMPLEMENTATION DEFINED.
0b0010 | Support for TCM only, Armv6 implementation.
0b0011 | Support for TCM and DMA, Armv6 implementation.

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

Access to this field is RO.

#### ShareLvl, bits [15:12]

Shareability Levels. Indicates the number of shareability levels implemented.

The value of this field is an IMPLEMENTATION DEFINED choice of:

ShareLvl | Meaning
--- | ---
0b0000 | One level of shareability implemented.
0b0001 | Two levels of shareability implemented.

All other values are reserved.

From Armv8 the only permitted value is 0b0001.

Access to this field is RO.

#### OuterShr, bits [11:8]

Outermost Shareability. Indicates the outermost shareability domain implemented.

The value of this field is an IMPLEMENTATION DEFINED choice of:

OuterShr | Meaning
--- | ---
0b0000 | Implemented as Non-cacheable.
0b0001 | Implemented with hardware coherency support.
0b1111 | Shareability ignored.

All other values are reserved.

From Armv8 the permitted values are 0b0000, 0b0001, and 0b1111.

Access to this field is RO.

#### PMSA, bits [7:4]

Indicates support for a PMSA.

The value of this field is an IMPLEMENTATION DEFINED choice of:

PMSA | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | Support for IMPLEMENTATION DEFINED PMSA.
0b0010 | Support for PMSAv6, with a Cache Type Register implemented.
0b0011 | Support for PMSAv7, with support for memory subsections. Armv7-R profile.

All other values are reserved.

In Armv8-A the only permitted value is 0b0000.

Access to this field is RO.

#### VMSA, bits [3:0]

Indicates support for a VMSA.

The value of this field is an IMPLEMENTATION DEFINED choice of:

VMSA | Meaning
--- | ---
0b0000 | Not supported.
0b0001 | Support for IMPLEMENTATION DEFINED VMSA.
0b0010 | Support for VMSAv6, with Cache and TLB Type Registers implemented.
0b0011 | Support for VMSAv7, with support for remapping and the Access flag. Armv7-A profile.
0b0100 | As for 0b0011, and adds support for the PXN bit in the Short-descriptor translation table format descriptors.
0b0101 | As for 0b0100, and adds support for the Long-descriptor translation table format.

All other values are reserved.

In Armv8-A the only permitted value is 0b0101.

Access to this field is RO.

### Otherwise:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
UNKNOWN
UNKNOWN

#### Bits [63:0]

Reserved, UNKNOWN.

## Accessing ID_MMFR0_EL1

Accesses to this register use the following encodings in the System register encoding space:

#### MRS <Xt>, ID_MMFR0_EL1

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b000 | 0b0000 | 0b0001 | 0b100

if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_MMFR0_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_MMFR0_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_MMFR0_EL1;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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