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# TRCITEEDCR, Instrumentation Trace Extension External Debug Control Register

The TRCITEEDCR characteristics are:

## Purpose

Controls instrumentation trace filtering.

## Configuration

External register TRCITEEDCR bits [31:0] are architecturally mapped to AArch64 System register TRCITEEDCR[31:0].

This register is present only when FEAT_ETE is implemented, FEAT_TRC_EXT is implemented and FEAT_ITE is implemented. Otherwise, direct accesses to TRCITEEDCR are RES0.

## Attributes

TRCITEEDCR is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | RL | S | NS | E3 | E2 | E1 | E0

#### Bits [31:7]

Reserved, RES0.

#### RL, bit [6]
When FEAT_RME is implemented:

Instrumentation Trace in Realm state.

RL | Meaning
--- | ---
0b0 | Instrumentation trace prohibited in Realm state.
0b1 | Instrumentation trace permitted in Realm state.

This field is ignored when SelfHostedTraceEnabled() returns TRUE.

This field is used in conjunction with TRCCONFIGR.ITO and TRCITEEDCR.E<m> to control whether Instrumentation trace is permitted or prohibited in Realm state.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### S, bit [5]
When Secure state is implemented:

Instrumentation Trace in Secure state.

S | Meaning
--- | ---
0b0 | Instrumentation trace prohibited in Secure state.
0b1 | Instrumentation trace permitted in Secure state.

This field is ignored when SelfHostedTraceEnabled() returns TRUE.

When FEAT_RME is not implemented, this field is used in conjunction with TRCCONFIGR.ITO, TRCITEEDCR.E3, and TRCITEEDCR.E<m> to control whether Instrumentation trace is permitted or prohibited in Secure state.

When FEAT_RME is implemented, this field is used in conjunction with TRCCONFIGR.ITO and TRCITEEDCR.E<m> to control whether Instrumentation trace is permitted or prohibited in Secure state.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### NS, bit [4]
When Non-secure state is implemented:

Instrumentation Trace in Non-secure state.

NS | Meaning
--- | ---
0b0 | Instrumentation trace prohibited in Non-secure state.
0b1 | Instrumentation trace permitted in Non-secure state.

This field is ignored when SelfHostedTraceEnabled() returns TRUE.

This field is used in conjunction with TRCCONFIGR.ITO and TRCITEEDCR.E<m> to control whether Instrumentation trace is permitted or prohibited in Non-secure state.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### E3, bit [3]
When EL3 is implemented:

Instrumentation Trace Enable at EL3.

E3 | Meaning
--- | ---
0b0 | Instrumentation trace prohibited at EL3.
0b1 | Instrumentation trace permitted at EL3.

This field is ignored when SelfHostedTraceEnabled() returns TRUE.

When FEAT_RME is not implemented, TRCITEEDCR.E3 is used in conjunction with TRCCONFIGR.ITO and TRCITEEDCR.S to control whether Instrumentation trace is permitted or prohibited at EL3.

When FEAT_RME is implemented, TRCITEEDCR.E3 is used in conjunction with TRCCONFIGR.ITO to control whether Instrumentation trace is permitted or prohibited at EL3.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### E<m>, bit [m], for m = 2 to 0

Instrumentation Trace Enable at EL<m>.

E<m> | Meaning
--- | ---
0b0 | Instrumentation trace prohibited at EL<m>.
0b1 | Instrumentation trace permitted at EL<m>.

This field is ignored when SelfHostedTraceEnabled() returns TRUE.

This bit is used in conjunction with TRCCONFIGR.ITO, TRCITEEDCR.NS, TRCITEEDCR.S, and TRCITEEDCR.RL to control whether Instrumentation trace is permitted or prohibited at EL<m> in the specified Security states.

TRCITEEDCR.E<2> is RES0 if EL2 is not implemented in any Security states.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

## Accessing TRCITEEDCR

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

#### TRCITEEDCR can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
ETE | 0x048 | TRCITEEDCR

This interface is accessible as follows:

- When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered(), accesses to this register generate an error response.
- Otherwise, accesses to this register are RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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