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# CTIPIDR2, CTI Peripheral Identification Register 2

The CTIPIDR2 characteristics are:

## Purpose

Provides information to identify a CTI component.

For more information, see 'About the Peripheral identification scheme'.

## Configuration

CTIPIDR2 is in the Debug power domain.

Implementation of this register is OPTIONAL.

This register is required for CoreSight compliance.

## Attributes

CTIPIDR2 is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | REVISION | JEDEC | DES_1

#### Bits [31:8]

Reserved, RES0.

#### REVISION, bits [7:4]

Part major revision. Parts can also use this field to extend Part number to 16-bits.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### JEDEC, bit [3]

Indicates a JEP106 identity code is used.

Reads as 0b1.

Access to this field is RO.

#### DES_1, bits [2:0]

Designer, most significant bits of JEP106 ID code. For Arm Limited, this field is 0b011.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

## Accessing CTIPIDR2

#### CTIPIDR2 can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
CTI | 0xFE8 | CTIPIDR2

Accesses on this interface are RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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