Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## LD1W (scalar plus scalar, single register)

Contiguous load unsigned words to vector (scalar index)

Contiguous load of unsigned words to elements of a vector register from the memory address generated by a 64-bit scalar base and scalar index which is multiplied by 4 and added to the base address. After each element access the index value is incremented, but the index register is not updated. Inactive elements will not cause a read from Device memory or signal a fault, and are set to zero in the destination vector.

It has encodings from 3 classes: 32-bit element , 64-bit element and 128-bit element

### 32-bit element

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | Rm | 0 | 1 | 0 | Pg | Rn | Zt
| dtype<3:1> | dtype<0> |  |  |  |  |

####

LD1W { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]

if !HaveSVE() && !HaveSME() then UNDEFINED; if Rm == '11111' then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt(Pg); constant integer esize = 32; constant integer msize = 32; boolean unsigned = TRUE;

### 64-bit element

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | Rm | 0 | 1 | 0 | Pg | Rn | Zt
| dtype<3:1> | dtype<0> |  |  |  |  |

####

LD1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]

if !HaveSVE() && !HaveSME() then UNDEFINED; if Rm == '11111' then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 32; boolean unsigned = TRUE;

### 128-bit element
(FEAT_SVE2p1)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | Rm | 1 | 0 | 0 | Pg | Rn | Zt
| dtype<1> | dtype<0> |  |  |  |  |  |

####

LD1W { <Zt>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]

if !HaveSVE2p1() then UNDEFINED; if Rm == '11111' then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer m = UInt(Rm); integer g = UInt(Pg); constant integer esize = 128; constant integer msize = 32; boolean unsigned = TRUE;

### Assembler Symbols

<Zt> | Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xm> | Is the 64-bit name of the general-purpose offset register, encoded in the "Rm" field.

### Operation

if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(64) base; bits(PL) mask = P[g, PL]; bits(VL) result; bits(msize) data; bits(64) offset; constant integer mbytes = msize DIV 8; boolean contiguous = TRUE; boolean nontemporal = FALSE; boolean tagchecked = TRUE; AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n, 64]; offset = X[m, 64]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then bits(64) addr = base + (UInt(offset) + e) * mbytes; data = Mem[addr, mbytes, accdesc]; Elem[result, e, esize] = Extend(data, esize, unsigned); else Elem[result, e, esize] = Zeros(esize); Z[t, VL] = result;

### Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored when its governing predicate register contains the same value for each execution.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.64, AdvSIMD v29.12, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T19:42

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