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# PMXEVTYPER_EL0, Performance Monitors Selected Event Type Register

The PMXEVTYPER_EL0 characteristics are:

## Purpose

When PMSELR_EL0.SEL selects an event counter, this accesses a PMEVTYPER<n>_EL0 register. When PMSELR_EL0.SEL selects the cycle counter, this accesses PMCCFILTR_EL0.

## Configuration

AArch64 System register PMXEVTYPER_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMXEVTYPER[31:0].

This register is present only when FEAT_PMUv3 is implemented. Otherwise, direct accesses to PMXEVTYPER_EL0 are UNDEFINED.

## Attributes

PMXEVTYPER_EL0 is a 64-bit register.

## Field descriptions

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Event type register or PMCCFILTR_EL0
Event type register or PMCCFILTR_EL0

#### Bits [63:0]

When PMSELR_EL0.SEL == 31, this register accesses PMCCFILTR_EL0.

Otherwise, this register accesses PMEVTYPER<n>_EL0 where n is the value in PMSELR_EL0.SEL.

The reset behavior of this field is:

- On a Warm reset, this field resets to an architecturally UNKNOWN value.

## Accessing PMXEVTYPER_EL0

If FEAT_FGT is implemented, and PMSELR_EL0.SEL is not 31 and is greater than or equal to the number of accessible event counters, then the behavior of permitted reads and writes of PMXEVTYPER_EL0 is as follows:

- If PMSELR_EL0.SEL selects an unimplemented event counter, the access is UNDEFINED.
- Otherwise, the access is trapped to EL2.

If FEAT_FGT is not implemented, and PMSELR_EL0.SEL is not 31 and is greater than or equal to the number of accessible event counters, then reads and writes of PMXEVTYPER_EL0 are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:

- Accesses to the register are UNDEFINED.
- Accesses to the register behave as RAZ/WI.
- Accesses to the register execute as a NOP.
- Accesses to the register behave as if PMSELR_EL0.SEL has an UNKNOWN value less than the number of event counters accessible at the current Exception level and Security state.
- Accesses to the register behave as if PMSELR_EL0.SEL is 31.
- If EL2 is implemented and enabled in the current Security state, PMSELR_EL0 is less than the number of implemented event counters, accesses from EL1 or permitted accesses from EL0 are trapped to EL2.

Permitted reads and writes of PMXEVTYPER_EL0 are RAZ/WI if all of the following are true:

- FEAT_PMUv3p9 is implemented.
- PSTATE.EL == EL0.
- PMUSERENR_EL0.UEN == 1.
- Any of the following are true:
  - PMSELR_EL0.SEL != 31 and PMUACR_EL1.P<UInt(PMSELR_EL0.SEL)> == 0.
  - PMSELR_EL0.SEL == 31 and PMUACR_EL1.C == 0.

Permitted writes of PMXEVTYPER_EL0 are ignored if all of the following are true:

- FEAT_PMUv3p9 is implemented.
- PSTATE.EL == EL0.
- PMUSERENR_EL0.UEN == 1.
- Any of the following are true:
  - PMSELR_EL0.SEL != 31 and PMUSERENR_EL0.ER == 1.
  - PMSELR_EL0.SEL == 31 and PMUSERENR_EL0.CR == 1.

Note

In EL0, an access is permitted if it is enabled by PMUSERENR_EL0.{UEN,EN}.

If EL2 is implemented and enabled in the current Security state, in EL1 and EL0, MDCR_EL2.HPMN identifies the number of accessible event counters. Otherwise, the number of accessible event counters is the number of implemented event counters. For more information, see MDCR_EL2.HPMN.

Accesses to this register use the following encodings in the System register encoding space:

#### MRS <Xt>, PMXEVTYPER_EL0

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b1001 | 0b1101 | 0b001

if UInt(PMSELR_EL0.SEL) != 31 && UInt(PMSELR_EL0.SEL) >= NUM_PMU_COUNTERS then if IsFeatureImplemented(FEAT_FGT) then UNDEFINED; else ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0.UEN == '0') then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMEVTYPERn_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && UInt(PMSELR_EL0.SEL) != 31 && UInt(PMSELR_EL0.SEL) >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.UEN == '1' && ((UInt(PMSELR_EL0.SEL) != 31 && PMUACR_EL1[UInt(PMSELR_EL0.SEL)] == '0') || (UInt(PMSELR_EL0.SEL) == 31 && PMUACR_EL1.C == '0')) then X[t, 64] = Zeros(64); elsif UInt(PMSELR_EL0.SEL) == 31 then X[t, 64] = PMCCFILTR_EL0; else X[t, 64] = PMEVTYPER_EL0[UInt(PMSELR_EL0.SEL)]; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMEVTYPERn_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && UInt(PMSELR_EL0.SEL) != 31 && UInt(PMSELR_EL0.SEL) >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif UInt(PMSELR_EL0.SEL) == 31 then X[t, 64] = PMCCFILTR_EL0; else X[t, 64] = PMEVTYPER_EL0[UInt(PMSELR_EL0.SEL)]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif UInt(PMSELR_EL0.SEL) == 31 then X[t, 64] = PMCCFILTR_EL0; else X[t, 64] = PMEVTYPER_EL0[UInt(PMSELR_EL0.SEL)]; elsif PSTATE.EL == EL3 then if UInt(PMSELR_EL0.SEL) == 31 then X[t, 64] = PMCCFILTR_EL0; else X[t, 64] = PMEVTYPER_EL0[UInt(PMSELR_EL0.SEL)];

#### MSR PMXEVTYPER_EL0, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b1001 | 0b1101 | 0b001

if UInt(PMSELR_EL0.SEL) != 31 && UInt(PMSELR_EL0.SEL) >= NUM_PMU_COUNTERS then if IsFeatureImplemented(FEAT_FGT) then UNDEFINED; else ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0.UEN == '0') then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMEVTYPERn_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && UInt(PMSELR_EL0.SEL) != 31 && UInt(PMSELR_EL0.SEL) >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.UEN == '1' && ((UInt(PMSELR_EL0.SEL) != 31 && (PMUACR_EL1[UInt(PMSELR_EL0.SEL)] == '0' || PMUSERENR_EL0.ER == '1')) || (UInt(PMSELR_EL0.SEL) == 31 && (PMUACR_EL1.C == '0' || PMUSERENR_EL0.CR == '1'))) then return; elsif UInt(PMSELR_EL0.SEL) == 31 then PMCCFILTR_EL0 = X[t, 64]; else PMEVTYPER_EL0[UInt(PMSELR_EL0.SEL)] = X[t, 64]; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMEVTYPERn_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && UInt(PMSELR_EL0.SEL) != 31 && UInt(PMSELR_EL0.SEL) >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); else AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif UInt(PMSELR_EL0.SEL) == 31 then PMCCFILTR_EL0 = X[t, 64]; else PMEVTYPER_EL0[UInt(PMSELR_EL0.SEL)] = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif UInt(PMSELR_EL0.SEL) == 31 then PMCCFILTR_EL0 = X[t, 64]; else PMEVTYPER_EL0[UInt(PMSELR_EL0.SEL)] = X[t, 64]; elsif PSTATE.EL == EL3 then if UInt(PMSELR_EL0.SEL) == 31 then PMCCFILTR_EL0 = X[t, 64]; else PMEVTYPER_EL0[UInt(PMSELR_EL0.SEL)] = X[t, 64];

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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