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# TRCCONFIGR, Trace Configuration Register

The TRCCONFIGR characteristics are:

## Purpose

Controls the tracing options.

## Configuration

External register TRCCONFIGR bits [31:0] are architecturally mapped to AArch64 System register TRCCONFIGR[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCCONFIGR are RES0.

## Attributes

TRCCONFIGR is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | ITO | RES0 | VMIDOPT | QE | RS | TS | RES0 | VMID | CID | RES0 | CCI | BB | RES0 | RES1

#### Bits [31:19]

Reserved, RES0.

#### ITO, bit [18]
When TRCIDR0.ITE == 1:

Instrumentation Trace Override.

ITO | Meaning
--- | ---
0b0 | Instrumentation Trace Override disabled.
0b1 | Instrumentation Trace Override enabled.

This field is ignored when SelfHostedTraceEnabled() returns TRUE.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bits [17:16]

Reserved, RES0.

#### VMIDOPT, bit [15]
When TRCIDR2.VMIDOPT == 0b01:

Virtual context identifier selection control.

VMIDOPT | Meaning
--- | ---
0b0 | VTTBR_EL2.VMID is used as the Virtual context identifier.
0b1 | CONTEXTIDR_EL2.PROCID is used as the Virtual context identifier.

####
When TRCIDR2.VMIDOPT == 0b00:

Reserved, RES0.

Virtual context identifier selection control.

VTTBR_EL2.VMID is used as the Virtual context identifier.

####
When TRCIDR2.VMIDOPT == 0b10:

Reserved, RES1.

Virtual context identifier selection control.

CONTEXTIDR_EL2.PROCID is used as the Virtual context identifier.

####
Otherwise:

Reserved, RES0.

#### QE, bits [14:13]
When TRCIDR0.QSUPP == 0b01:

Q element generation control.

QE | Meaning
--- | ---
0b00 | Q elements are disabled.
0b01 | Q elements with instruction counts are enabled. Q elements without instruction counts are disabled.

All other values are reserved.

####
When TRCIDR0.QSUPP == 0b10:

Q element generation control.

QE | Meaning
--- | ---
0b00 | Q elements are disabled.
0b11 | Q elements with instruction counts are enabled. Q elements without instruction counts are enabled.

All other values are reserved.

####
When TRCIDR0.QSUPP == 0b11:

Q element generation control.

QE | Meaning
--- | ---
0b00 | Q elements are disabled.
0b01 | Q elements with instruction counts are enabled. Q elements without instruction counts are disabled.
0b11 | Q elements with instruction counts are enabled. Q elements without instruction counts are enabled.

All other values are reserved.

####
Otherwise:

Reserved, RES0.

#### RS, bit [12]
When TRCIDR0.RETSTACK == 1:

Return stack control.

RS | Meaning
--- | ---
0b0 | Return stack is disabled.
0b1 | Return stack is enabled.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### TS, bit [11]
When TRCIDR0.TSSIZE != 0b00000:

Global timestamp tracing control.

TS | Meaning
--- | ---
0b0 | Global timestamp tracing is disabled.
0b1 | Global timestamp tracing is enabled.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bits [10:8]

Reserved, RES0.

#### VMID, bit [7]
When TRCIDR2.VMIDSIZE != 0b00000:

Virtual context identifier tracing control.

VMID | Meaning
--- | ---
0b0 | Virtual context identifier tracing is disabled.
0b1 | Virtual context identifier tracing is enabled.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### CID, bit [6]
When TRCIDR2.CIDSIZE != 0b00000:

Context identifier tracing control.

CID | Meaning
--- | ---
0b0 | Context identifier tracing is disabled.
0b1 | Context identifier tracing is enabled.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bit [5]

Reserved, RES0.

#### CCI, bit [4]
When TRCIDR0.TRCCCI == 1:

Cycle counting instruction tracing control.

CCI | Meaning
--- | ---
0b0 | Cycle counting instruction tracing is disabled.
0b1 | Cycle counting instruction tracing is enabled.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### BB, bit [3]
When TRCIDR0.TRCBB == 1:

Branch broadcasting control.

BB | Meaning
--- | ---
0b0 | Branch broadcasting is disabled.
0b1 | Branch broadcasting is enabled.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

####
Otherwise:

Reserved, RES0.

#### Bits [2:1]

Reserved, RES0.

#### Bit [0]

Reserved, RES1.

## Accessing TRCCONFIGR

Must always be programmed.

TRCCONFIGR.QE must be set to 0b00 if TRCCONFIGR.BB is not 0.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

#### TRCCONFIGR can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
ETE | 0x010 | TRCCONFIGR

This interface is accessible as follows:

- When OSLockStatus(), or !IsTraceCorePowered() or !AllowExternalTraceAccess(), accesses to this register generate an error response.
- Otherwise, accesses to this register are RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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