AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

# GICR_VPROPBASER, Virtual Redistributor Properties Base Address Register

The GICR_VPROPBASER characteristics are:

## Purpose

In GICv4.0, specifies the base address of the memory that holds the virtual LPI Configuration table for the currently scheduled virtual machine.

In GICv4.1, specifies the base address of the memory that holds the vPE Configuration table.

## Configuration

This register is provided in FEAT_GICv4 implementations only.

## Attributes

GICR_VPROPBASER is a 64-bit register.

## Field descriptions

### When GICv4.1 is implemented:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Valid | RES0 | Entry_Size | OuterCache | Indirect | Page_Size | Z | Physical_Address
Physical_Address | Shareability | InnerCache | Size

#### Valid, bit [63]

This bit controls whether the vPE Configuration Table is valid.

Valid | Meaning
--- | ---
0b0 | The vPE Configuration table is not valid.
0b1 | The vPE Configuration table is valid.

The reset behavior of this field is:

- On a GIC reset, this field resets to 0.

#### Bit [62]

Reserved, RES0.

#### Entry_Size, bits [61:59]

Specifies the number 64-bit doublewords per table entry, minus one.

This bit is read-only.

#### OuterCache, bits [58:56]

Indicates the Outer Cacheability attributes of accesses to the table.

OuterCache | Meaning
--- | ---
0b000 | Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability.
0b001 | Normal Outer Non-cacheable.
0b010 | Normal Outer Cacheable Read-allocate, Write-through.
0b011 | Normal Outer Cacheable Read-allocate, Write-back.
0b100 | Normal Outer Cacheable Write-allocate, Write-through.
0b101 | Normal Outer Cacheable Write-allocate, Write-back.
0b110 | Normal Outer Cacheable Read-allocate, Write-allocate, Write-through.
0b111 | Normal Outer Cacheable Read-allocate, Write-allocate, Write-back.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

The reset behavior of this field is:

- On a GIC reset, this field resets to an UNKNOWN value.

#### Indirect, bit [55]

This field indicates whether GICR_VPROPBASER specifies a single, flat table or a two-level table where the first level contains a list of descriptors.

Indirect | Meaning
--- | ---
0b0 | Single Level. The Size field indicates the number of pages used to store data associated with each table entry.
0b1 | Two Level. The Size field indicates the number of pages that contain an array of 64-bit descriptors to pages that are used to store the data associated with each table entry. A little endian memory order model is used.

This field is RAZ/WI for GIC implementations that only support flat tables.

If the supported vPEID width indicated by GICD_TYPER2.VIL and GICD_TYPER2.VID, and the smallest page size that is supported result in a single level table that requires multiple pages, then implementing this bit as RAZ/WI is deprecated.

The reset behavior of this field is:

- On a GIC reset, this field resets to an UNKNOWN value.

#### Page_Size, bits [54:53]

The following values indicate the size of page that the translation table uses:

Page_Size | Meaning
--- | ---
0b00 | 4KB.
0b01 | 16KB.
0b10 | 64KB.
0b11 | Reserved. Treated as 0b10.

Note

If the GIC implementation supports only a single, fixed page size, this field might be RO.

The reset behavior of this field is:

- On a GIC reset, this field resets to an UNKNOWN value.

#### Z, bit [52]

When GICR_VPROPBASER.Valid is written from 0 to 1, GICR_VPROPBASER.Z indicates whether the vPE Configuration table is known to contain all zeros.

Z | Meaning
--- | ---
0b0 | The vPE Configutation table is not zero, and contains live data.
0b1 | The vPE Configuration table is zero.

Setting GICR_VPROPBASER.Z to 0 causes the IRI to reload configuration from memory

When GICR_VPROPBASER.Valid is written from 0 to 1, if GICR_VPROPBASER.Z==1 behavior is UNPREDICTABLE if the allocated memory does not contain all zeros.

This field is WO, and reads as 0.

#### Physical_Address, bits [51:12]

Bits [51:12] of the physical address containing the LPI Configuration table.

In implementations supporting fewer than 52 bits of physical address, unimplemented upper bits are RES0.

The reset behavior of this field is:

- On a GIC reset, this field resets to an UNKNOWN value.

#### Shareability, bits [11:10]

Indicates the Shareability attributes of accesses to the LPI Configuration table.

Shareability | Meaning
--- | ---
0b00 | Non-shareable.
0b01 | Inner Shareable.
0b10 | Outer Shareable.
0b11 | Reserved. Treated as 0b00.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

The reset behavior of this field is:

- On a GIC reset, this field resets to an UNKNOWN value.

#### InnerCache, bits [9:7]

Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table.

InnerCache | Meaning
--- | ---
0b000 | Device-nGnRnE.
0b001 | Normal Inner Non-cacheable.
0b010 | Normal Inner Cacheable Read-allocate, Write-through.
0b011 | Normal Inner Cacheable Read-allocate, Write-back.
0b100 | Normal Inner Cacheable Write-allocate, Write-through.
0b101 | Normal Inner Cacheable Write-allocate, Write-back.
0b110 | Normal Inner Cacheable Read-allocate, Write-allocate, Write-through.
0b111 | Normal Inner Cacheable Read-allocate, Write-allocate, Write-back.

The reset behavior of this field is:

- On a GIC reset, this field resets to an UNKNOWN value.

#### Size, bits [6:0]

The number of pages of physical memory allocated to the table, minus one.

GICR_VPROPBASER.Page_Size specifies the size of each page.

The reset behavior of this field is:

- On a GIC reset, this field resets to an UNKNOWN value.

### When GICv4 is implemented:

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | OuterCache | RES0 | Physical_Address
Physical_Address | Shareability | InnerCache | RES0 | IDbits

#### Bits [63:59]

Reserved, RES0.

#### OuterCache, bits [58:56]

Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table.

OuterCache | Meaning
--- | ---
0b000 | Memory type defined in InnerCache field. For Normal memory, Outer Cacheability is the same as Inner Cacheability.
0b001 | Normal Outer Non-cacheable.
0b010 | Normal Outer Cacheable Read-allocate, Write-through.
0b011 | Normal Outer Cacheable Read-allocate, Write-back.
0b100 | Normal Outer Cacheable Write-allocate, Write-through.
0b101 | Normal Outer Cacheable Write-allocate, Write-back.
0b110 | Normal Outer Cacheable Read-allocate, Write-allocate, Write-through.
0b111 | Normal Outer Cacheable Read-allocate, Write-allocate, Write-back.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

The reset behavior of this field is:

- On a GIC reset, this field resets to an architecturally UNKNOWN value.

#### Bits [55:52]

Reserved, RES0.

#### Physical_Address, bits [51:12]

Bits [51:12] of the physical address containing the virtual LPI Configuration table.

In implementations supporting fewer than 52 bits of physical address, unimplemented upper bits are RES0.

The reset behavior of this field is:

- On a GIC reset, this field resets to an architecturally UNKNOWN value.

#### Shareability, bits [11:10]

Indicates the Shareability attributes of accesses to the LPI Configuration table.

Shareability | Meaning
--- | ---
0b00 | Non-shareable.
0b01 | Inner Shareable.
0b10 | Outer Shareable.
0b11 | Reserved. Treated as 0b00.

It is IMPLEMENTATION DEFINED whether this field has a fixed value or can be programmed by software. Implementing this field with a fixed value is deprecated.

The reset behavior of this field is:

- On a GIC reset, this field resets to an architecturally UNKNOWN value.

#### InnerCache, bits [9:7]

Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table.

InnerCache | Meaning
--- | ---
0b000 | Device-nGnRnE.
0b001 | Normal Inner Non-cacheable.
0b010 | Normal Inner Cacheable Read-allocate, Write-through.
0b011 | Normal Inner Cacheable Read-allocate, Write-back.
0b100 | Normal Inner Cacheable Write-allocate, Write-through.
0b101 | Normal Inner Cacheable Write-allocate, Write-back.
0b110 | Normal Inner Cacheable Read-allocate, Write-allocate, Write-through.
0b111 | Normal Inner Cacheable Read-allocate, Write-allocate, Write-back.

The reset behavior of this field is:

- On a GIC reset, this field resets to an architecturally UNKNOWN value.

#### Bits [6:5]

Reserved, RES0.

#### IDbits, bits [4:0]

The number of bits of virtual LPI INTID supported, minus one.

If the value of this field is less than 0b1101, indicating that the largest INTID is less than 8192 (the smallest LPI interrupt ID), the GIC will behave as if all virtual LPIs are out of range.

The reset behavior of this field is:

- On a GIC reset, this field resets to an architecturally UNKNOWN value.

## Accessing GICR_VPROPBASER

#### GICR_VPROPBASER can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
GIC Redistributor | VLPI_base | 0x0070 | GICR_VPROPBASER

Accesses on this interface are RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.