Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## EXTQ

Extract vector segment from each pair of quadword vector segments

For each 128-bit vector segment of the result, copy the indexed byte up to and including the last byte of the corresponding first source vector segment to the bottom of the result segment, then fill the remainder of the result segment starting from the first byte of the corresponding second source vector segment. The result segments are destructively placed in the corresponding first source vector segment. This instruction is unpredicated.

### SVE2
(FEAT_SVE2p1)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | imm4 | 0 | 0 | 1 | 0 | 0 | 1 | Zm | Zdn

####

EXTQ <Zdn>.B, <Zdn>.B, <Zm>.B, #<imm>

if !HaveSVE2p1() && !HaveSME2p1() then UNDEFINED; integer dn = UInt(Zdn); integer m = UInt(Zm); constant integer position = UInt(imm4) << 3;

### Assembler Symbols

<Zdn> | Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.

<Zm> | Is the name of the second source scalable vector register, encoded in the "Zm" field.

<imm> | Is the unsigned immediate operand, in the range 0 to 15, encoded in the "imm4" field.

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer segments = VL DIV 128; bits(VL) operand1 = Z[dn, VL]; bits(VL) operand2 = Z[m, VL]; bits(VL) result; for s = 0 to segments-1 bits(256) concat = Elem[operand2, s, 128] : Elem[operand1, s, 128]; Elem[result, s, 128] = concat<position+127:position>; Z[dn, VL] = result;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX instruction must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is unpredictable:

- The MOVPRFX instruction must be unpredicated.
- The MOVPRFX instruction must specify the same destination register as this instruction.
- The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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