Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## CRC32CB, CRC32CH, CRC32CW, CRC32CX

CRC32C checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation.

In an Armv8.0 implementation, this is an OPTIONAL instruction. From Armv8.1, it is mandatory for all implementations to implement this instruction.

#### Note

ID_AA64ISAR0_EL1.CRC32 indicates whether this instruction is supported.

### CRC
(FEAT_CRC32)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
sf | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | Rm | 0 | 1 | 0 | 1 | sz | Rn | Rd
|  | S |  |  |  | C |  |  |

#### CRC32CB (sf == 0 && sz == 00)

CRC32CB <Wd>, <Wn>, <Wm>

#### CRC32CH (sf == 0 && sz == 01)

CRC32CH <Wd>, <Wn>, <Wm>

#### CRC32CW (sf == 0 && sz == 10)

CRC32CW <Wd>, <Wn>, <Wm>

#### CRC32CX (sf == 1 && sz == 11)

CRC32CX <Wd>, <Wn>, <Xm>

if !IsFeatureImplemented(FEAT_CRC32) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if sf == '1' && sz != '11' then UNDEFINED; if sf == '0' && sz == '11' then UNDEFINED; constant integer size = 8 << UInt(sz);

### Assembler Symbols

<Wd> | Is the 32-bit name of the general-purpose accumulator output register, encoded in the "Rd" field.

<Wn> | Is the 32-bit name of the general-purpose accumulator input register, encoded in the "Rn" field.

<Wm> | Is the 32-bit name of the general-purpose data source register, encoded in the "Rm" field.

<Xm> | Is the 64-bit name of the general-purpose data source register, encoded in the "Rm" field.

### Operation

bits(32) acc = X[n, 32]; // accumulator bits(size) val = X[m, size]; // input value bits(32) poly = 0x1EDC6F41<31:0>; bits(32+size) tempacc = BitReverse(acc):Zeros(size); bits(size+32) tempval = BitReverse(val):Zeros(32); // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation X[d, 32] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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