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# GICD_ICENABLER<n>E, Interrupt Clear-Enable Registers, n = 0 - 31

The GICD_ICENABLER<n>E characteristics are:

## Purpose

Disables forwarding of the corresponding SPI in the extended SPI range to the CPU interfaces.

## Configuration

This register is present only when GICv3.1 is implemented. Otherwise, direct accesses to GICD_ICENABLER<n>E are RES0.

When GICD_TYPER.ESPI==0, these registers are RES0.

When GICD_TYPER.ESPI==1, the number of implemented GICD_ICENABLER<n>E registers is (GICD_TYPER.ESPI_range+1). Registers are numbered from 0.

## Attributes

GICD_ICENABLER<n>E is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Clear_enable_bit31 | Clear_enable_bit30 | Clear_enable_bit29 | Clear_enable_bit28 | Clear_enable_bit27 | Clear_enable_bit26 | Clear_enable_bit25 | Clear_enable_bit24 | Clear_enable_bit23 | Clear_enable_bit22 | Clear_enable_bit21 | Clear_enable_bit20 | Clear_enable_bit19 | Clear_enable_bit18 | Clear_enable_bit17 | Clear_enable_bit16 | Clear_enable_bit15 | Clear_enable_bit14 | Clear_enable_bit13 | Clear_enable_bit12 | Clear_enable_bit11 | Clear_enable_bit10 | Clear_enable_bit9 | Clear_enable_bit8 | Clear_enable_bit7 | Clear_enable_bit6 | Clear_enable_bit5 | Clear_enable_bit4 | Clear_enable_bit3 | Clear_enable_bit2 | Clear_enable_bit1 | Clear_enable_bit0

#### Clear_enable_bit<x>, bit [x], for x = 31 to 0

For the extended SPI range, controls the forwarding of interrupt number x to the CPU interface. Reads and writes have the following behavior:

Clear_enable_bit<x> | Meaning
--- | ---
0b0 | If read, indicates that forwarding of the corresponding interrupt is disabled. If written, has no effect.
0b1 | If read, indicates that forwarding of the corresponding interrupt is enabled. If written, enables forwarding of the corresponding interrupt. After a write of 1 to this bit, a subsequent read of this bit returns 0.

The reset behavior of this field is:

- On a GIC reset, this field resets to 0.

#### Additional information

For INTID m, when DIV and MOD are the integer division and modulo operations:

- The corresponding GICD_ICENABLER<n>E number, n, is given by n = (m-4096) DIV 32.

- The offset of the required GICD_ICENABLER<n>E is (0x1400 + (4*n)).

- The bit number of the required group modifier bit in this register is (m-4096) MOD 32.

## Accessing GICD_ICENABLER<n>E

When affinity routing is not enabled for the Security state of an interrupt in GICD_ICENABLER<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure SPIs are RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

#### GICD_ICENABLER<n>E can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
GIC Distributor | Dist_base | 0x1400 + (4 * n) | GICD_ICENABLER<n>E

Accesses on this interface are RW.

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26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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