Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## F1CVT, F2CVT

8-bit floating-point convert to half-precision

Convert each even-numbered 8-bit floating-point element of the source vector to half-precision while downscaling the value, and place the results in the overlapping 16-bit elements of the destination vector. F1CVT scales the values by 2-UInt(FPMR.LSCALE[3:0]). F2CVT scales the values by 2-UInt(FPMR.LSCALE2[3:0]).

The 8-bit floating-point encoding format for F1CVT is selected by FPMR.F8S1. The 8-bit floating-point encoding format for F2CVT is selected by FPMR.F8S2.

This instruction is unpredicated.

It has encodings from 2 classes: F1CVT and F2CVT

### F1CVT
(FEAT_FP8)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | Zn | Zd
| L |  |  |  |  |

####

F1CVT <Zd>.H, <Zn>.B

if ((!IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME2)) || !IsFeatureImplemented(FEAT_FP8)) then UNDEFINED; constant integer esize = 16; constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 8; constant integer d_esize = 16; constant boolean issrc2 = FALSE;

### F2CVT
(FEAT_FP8)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | Zn | Zd
| L |  |  |  |  |

####

F2CVT <Zd>.H, <Zn>.B

if ((!IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME2)) || !IsFeatureImplemented(FEAT_FP8)) then UNDEFINED; constant integer esize = 16; constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 8; constant integer d_esize = 16; constant boolean issrc2 = TRUE;

### Assembler Symbols

<Zd> | Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Zn> | Is the name of the source scalable vector register, encoded in the "Zn" field.

### Operation

CheckFPMREnabled(); CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; constant bits(VL) operand = Z[n, VL]; bits(VL) result; for e = 0 to elements-1 constant bits(esize) element = Elem[operand, e, esize]; constant bits(d_esize) res = FP8ConvertFP(element<s_esize-1:0>, issrc2, FPCR, FPMR); Elem[result, e, esize] = ZeroExtend(res, esize); Z[d, VL] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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