Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## BRKN

Propagate break to next partition

If the last active element of the first source predicate is false then set the destination predicate to all-false. Otherwise leaves the destination and second source predicate unchanged. Does not set the condition flags.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | Pg | 0 | Pn | 0 | Pdm
| S |  |  |  |  |  |

####

BRKN <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B

if !HaveSVE() && !HaveSME() then UNDEFINED; integer g = UInt(Pg); integer n = UInt(Pn); integer dm = UInt(Pdm); boolean setflags = FALSE;

### Assembler Symbols

<Pdm> | Is the name of the second source and destination scalable predicate register, encoded in the "Pdm" field.

<Pg> | Is the name of the governing scalable predicate register, encoded in the "Pg" field.

<Pn> | Is the name of the first source scalable predicate register, encoded in the "Pn" field.

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; bits(PL) mask = P[g, PL]; bits(PL) operand1 = P[n, PL]; bits(PL) operand2 = P[dm, PL]; bits(PL) result; if LastActive(mask, operand1, 8) == '1' then result = operand2; else result = Zeros(PL); if setflags then PSTATE.<N,Z,C,V> = PredTest(Ones(PL), result, 8); P[dm, PL] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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