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# GICR_ISENABLER<n>E, Interrupt Set-Enable Registers, n = 1 - 2

The GICR_ISENABLER<n>E characteristics are:

## Purpose

Enables forwarding of the corresponding PPI to the CPU interfaces.

## Configuration

This register is present only when GICv3.1 is implemented. Otherwise, direct accesses to GICR_ISENABLER<n>E are RES0.

A copy of this register is provided for each Redistributor.

## Attributes

GICR_ISENABLER<n>E is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Set_enable_bit31 | Set_enable_bit30 | Set_enable_bit29 | Set_enable_bit28 | Set_enable_bit27 | Set_enable_bit26 | Set_enable_bit25 | Set_enable_bit24 | Set_enable_bit23 | Set_enable_bit22 | Set_enable_bit21 | Set_enable_bit20 | Set_enable_bit19 | Set_enable_bit18 | Set_enable_bit17 | Set_enable_bit16 | Set_enable_bit15 | Set_enable_bit14 | Set_enable_bit13 | Set_enable_bit12 | Set_enable_bit11 | Set_enable_bit10 | Set_enable_bit9 | Set_enable_bit8 | Set_enable_bit7 | Set_enable_bit6 | Set_enable_bit5 | Set_enable_bit4 | Set_enable_bit3 | Set_enable_bit2 | Set_enable_bit1 | Set_enable_bit0

#### Set_enable_bit<x>, bit [x], for x = 31 to 0

For the extended PPI range, controls the forwarding of interrupt number x to the CPU interface. Reads and writes have the following behavior:

Set_enable_bit<x> | Meaning
--- | ---
0b0 | If read, indicates that forwarding of the corresponding interrupt is disabled. If written, has no effect.
0b1 | If read, indicates that forwarding of the corresponding interrupt is enabled. If written, enables forwarding of the corresponding interrupt. After a write of 1 to this bit, a subsequent read of this bit returns 1.

The reset behavior of this field is:

- On a GIC reset, this field resets to 0.

#### Additional information

For INTID m, when DIV and MOD are the integer division and modulo operations:

- The corresponding GICR_ISENABLER<n>E number, n, is given by n = (m-1024) DIV 32.
- The offset of the required GICR_ISENABLER<n>E is (0x100 + (4*n)).
- The bit number of the required group modifier bit in this register is (m-1024) MOD 32.

## Accessing GICR_ISENABLER<n>E

When affinity routing is not enabled for the Security state of an interrupt in GICR_ISENABLER<n>E, the corresponding bit is RES0.

When GICD_CTLR.DS==0, bits corresponding to Secure PPIs are RAZ/WI to Non-secure accesses.

Bits corresponding to unimplemented interrupts are RAZ/WI.

#### GICR_ISENABLER<n>E can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
GIC Redistributor | SGI_base | 0x0100 + (4 * n) | GICR_ISENABLER<n>E

Accesses on this interface are RW.

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26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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