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# DC CIPAE, Data or unified Cache line Clean and Invalidate by PA to PoE

The DC CIPAE characteristics are:

## Purpose

Data or unified Cache line Clean and Invalidate by PA to PoE.

## Configuration

This instruction is present only when FEAT_MEC is implemented. Otherwise, direct accesses to DC CIPAE are UNDEFINED.

## Attributes

DC CIPAE is a 64-bit System instruction.

## Field descriptions

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NS | NSE | RES0 | PA[55:52] | PA
PA

#### NS, bit [63]

Together with the NSE field, this field specifies the target physical address space.

NSE | NS | Meaning
--- | --- | ---
0b0 | 0b0 | Reserved.
0b0 | 0b1 | Reserved.
0b1 | 0b0 | Reserved.
0b1 | 0b1 | Realm.

If {NSE, NS} != {0b1, 0b1}, then no cache entries are required to be cleaned or invalidated

#### NSE, bit [62]

Together with the NS field, this field specifies the target physical address space.

For a description of the values derived by evaluating NS and NSE together, see DC CIPAE.NS.

#### Bits [61:56]

Reserved, RES0.

#### PA[55:52], bits [55:52]
When FEAT_D128 is implemented:

Extension to PA[51:0] if ID_AA64MMFR0_EL1.PARange = 0111. For more information see PA[51:0].

####
Otherwise:

Reserved, RES0.

#### PA, bits [51:0]

Physical address to use. No alignment restrictions apply to this PA.

## Executing DC CIPAE

Accesses to this instruction use the following encodings in the System instruction encoding space:

#### DC CIPAE, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b01 | 0b100 | 0b0111 | 0b1110 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then if !IsCurrentSecurityState(SS_Realm) then UNDEFINED; else AArch64.DC(X[t, 64], CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoE); elsif PSTATE.EL == EL3 then AArch64.DC(X[t, 64], CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoE);

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26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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