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## STRB (immediate)

Store Register Byte (immediate) stores the least significant byte of a 32-bit register to memory. The address that is used for the store is calculated from a base register and an immediate offset. For information about memory accesses, see Load/Store addressing modes.

It has encodings from 3 classes: Post-index , Pre-index and Unsigned offset

### Post-index

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | imm9 | 0 | 1 | Rn | Rt
size |  |  |  | opc |  |  |  |  |

####

STRB <Wt>, [<Xn|SP>], #<simm>

boolean wback = TRUE; boolean postindex = TRUE; bits(64) offset = SignExtend(imm9, 64);

### Pre-index

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | imm9 | 1 | 1 | Rn | Rt
size |  |  |  | opc |  |  |  |  |

####

STRB <Wt>, [<Xn|SP>, #<simm>]!

boolean wback = TRUE; boolean postindex = FALSE; bits(64) offset = SignExtend(imm9, 64);

### Unsigned offset

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | imm12 | Rn | Rt
size |  |  |  | opc |  |  |

####

STRB <Wt>, [<Xn|SP>{, #<pimm>}]

boolean wback = FALSE; boolean postindex = FALSE; bits(64) offset = LSL(ZeroExtend(imm12, 64), 0);

For information about the constrained unpredictable behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly STRB (immediate).

### Assembler Symbols

<Wt> | Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<simm> | Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.

<pimm> | Is the optional positive immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.

### Shared Decode

integer n = UInt(Rn); integer t = UInt(Rt); boolean tagchecked = wback || n != 31; boolean rt_unknown = FALSE; Constraint c; if wback && n == t && n != 31 then c = ConstrainUnpredictable(Unpredictable_WBOVERLAPST); assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_NONE rt_unknown = FALSE; // value stored is original value when Constraint_UNKNOWN rt_unknown = TRUE; // value stored is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction();

### Operation

bits(64) address; bits(8) data; boolean privileged = PSTATE.EL != EL0; AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, FALSE, privileged, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; if !postindex then address = GenerateAddress(address, offset, accdesc); if rt_unknown then data = bits(8) UNKNOWN; else data = X[t, 8]; Mem[address, 1, accdesc] = data; if wback then if postindex then address = GenerateAddress(address, offset, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;

### Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

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Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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