Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## SDOT (by element)

Dot Product signed arithmetic (vector, by element). This instruction performs the dot product of the four 8-bit elements in each 32-bit element of the first source register with the four 8-bit elements of an indexed 32-bit element in the second source register, accumulating the result into the corresponding 32-bit element of the destination register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

In Armv8.2 and Armv8.3, this is an optional instruction. From Armv8.4 it is mandatory for all implementations to support it.

#### Note

ID_AA64ISAR0_EL1.DP indicates whether this instruction is supported.

### Vector
(FEAT_DotProd)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 0 | 0 | 1 | 1 | 1 | 1 | size | L | M | Rm | 1 | 1 | 1 | 0 | H | 0 | Rn | Rd
|  | U |  |  |  |  |  |  |  |  |  |

####

SDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.4B[<index>]

if !IsFeatureImplemented(FEAT_DotProd) then UNDEFINED; if size != '10' then UNDEFINED; boolean signed = (U == '0'); integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(M:Rm); integer index = UInt(H:L); constant integer esize = 8 << UInt(size); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize;

### Assembler Symbols

<Vd> | Is the name of the SIMD&FP third source and destination register, encoded in the "Rd" field.

<Ta> | Is an arrangement specifier, encoded in Q:
Q | <Ta>
--- | ---
0 | 2S
1 | 4S

<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Tb> | Is an arrangement specifier, encoded in Q:
Q | <Tb>
--- | ---
0 | 8B
1 | 16B

<Vm> | Is the name of the second SIMD&FP source register, encoded in the "M:Rm" fields.

<index> | Is the element index, encoded in the "H:L" fields.

### Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n, datasize]; bits(128) operand2 = V[m, 128]; bits(datasize) result = V[d, datasize]; for e = 0 to elements-1 integer res = 0; integer element1, element2; for i = 0 to 3 if signed then element1 = SInt(Elem[operand1, 4*e+i, esize DIV 4]); element2 = SInt(Elem[operand2, 4*index+i, esize DIV 4]); else element1 = UInt(Elem[operand1, 4*e+i, esize DIV 4]); element2 = UInt(Elem[operand2, 4*index+i, esize DIV 4]); res = res + element1 * element2; Elem[result, e, esize] = Elem[result, e, esize] + res; V[d, datasize] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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