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# GICD_TYPER, Interrupt Controller Type Register

The GICD_TYPER characteristics are:

## Purpose

Provides information about what features the GIC implementation supports. It indicates:

- Whether the GIC implementation supports two Security states.
- The maximum number of INTIDs that the GIC implementation supports.
- The number of PEs that can be used as interrupt targets.

## Configuration

This register is available in all configurations of the GIC. When GICD_CTLR.DS==0, this register is Common.

## Attributes

GICD_TYPER is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
ESPI_range | RSS | No1N | A3V | IDbits | DVIS | LPIS | MBIS | num_LPIs | SecurityExtn | NMI | ESPI | CPUNumber | ITLinesNumber

#### ESPI_range, bits [31:27]
When GICD_TYPER.ESPI == 1:

Indicates the maximum INTID in the Extended SPI range.

Maximum Extended SPI INTID is (32*(ESPI_range + 1) + 4095).

The ESPI_range field only indicates the maximum number of SPIs that the GIC implementation might support. This value determines the number of instances of the following interrupt registers:

- GICD_IGROUPR<n>E.
- GICD_ISENABLER<n>E.
- GICD_ICENABLER<n>E.
- GICD_ISPENDR<n>E.
- GICD_ICPENDR<n>E.
- GICD_ISACTIVER<n>E.
- GICD_ICACTIVER<n>E.
- GICD_IPRIORITYR<n>E.
- GICD_ICFGR<n>E.
- GICD_IROUTER<n>E.
- GICD_IGRPMODR<n>E.

The GIC architecture does not require a GIC implementation to support a continuous range of SPI interrupt IDs. Software must check which SPI INTIDs are supported, up to the maximum value indicated by GICD_TYPER.ESPI_range.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

####
Otherwise:

Reserved, RES0.

#### RSS, bit [26]

Range Selector Support.

The value of this field is an IMPLEMENTATION DEFINED choice of:

RSS | Meaning
--- | ---
0b0 | The IRI supports targeted SGIs with affinity level 0 values of 0 - 15.
0b1 | The IRI supports targeted SGIs with affinity level 0 values of 0 - 255.

Access to this field is RO.

#### No1N, bit [25]

Indicates whether 1 of N SPI interrupts are supported.

The value of this field is an IMPLEMENTATION DEFINED choice of:

No1N | Meaning
--- | ---
0b0 | 1 of N SPI interrupts are supported.
0b1 | 1 of N SPI interrupts are not supported.

Access to this field is RO.

#### A3V, bit [24]

Affinity 3 valid. Indicates whether the Distributor supports nonzero values of Affinity level 3.

The value of this field is an IMPLEMENTATION DEFINED choice of:

A3V | Meaning
--- | ---
0b0 | The Distributor only supports zero values of Affinity level 3.
0b1 | The Distributor supports nonzero values of Affinity level 3.

Access to this field is RO.

#### IDbits, bits [23:19]

The number of interrupt identifier bits supported, minus one.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### DVIS, bit [18]
When GICv4 is implemented:

Indicates whether the implementation supports Direct Virtual LPI injection.

The value of this field is an IMPLEMENTATION DEFINED choice of:

DVIS | Meaning
--- | ---
0b0 | The implementation does not support Direct Virtual LPI injection.
0b1 | The implementation supports Direct Virtual LPI injection.

Access to this field is RO.

####
Otherwise:

Reserved, RES0.

#### LPIS, bit [17]

Indicates whether the implementation supports LPIs.

The value of this field is an IMPLEMENTATION DEFINED choice of:

LPIS | Meaning
--- | ---
0b0 | The implementation does not support LPIs.
0b1 | The implementation supports LPIs.

Access to this field is RO.

#### MBIS, bit [16]

Indicates whether the implementation supports message-based interrupts by writing to Distributor registers.

The value of this field is an IMPLEMENTATION DEFINED choice of:

MBIS | Meaning
--- | ---
0b0 | The implementation does not support message-based interrupts by writing to Distributor registers. The GICD_CLRSPI_NSR, GICD_SETSPI_NSR, GICD_CLRSPI_SR, and GICD_SETSPI_SR registers are reserved.
0b1 | The implementation supports message-based interrupts by writing to the GICD_CLRSPI_NSR, GICD_SETSPI_NSR, GICD_CLRSPI_SR, or GICD_SETSPI_SR registers.

Access to this field is RO.

#### num_LPIs, bits [15:11]

Number of supported LPIs.

- 0b00000 Number of LPIs as indicated by GICD_TYPER.IDbits.

- All other values Number of LPIs supported is 2(num_LPIs+1).

  - Available LPI INTIDs are 8192..(8192 + 2(num_LPIs+1) - 1).

  - This field cannot indicate a maximum LPI INTID greater than that indicated by GICD_TYPER.IDbits.

When the supported INTID width is less than 14 bits, this field is RES0 and no LPIs are supported.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### SecurityExtn, bit [10]

Indicates whether the GIC implementation supports two Security states:

When GICD_CTLR.DS == 1, this field is RAZ.

The value of this field is an IMPLEMENTATION DEFINED choice of:

SecurityExtn | Meaning
--- | ---
0b0 | The GIC implementation supports only a single Security state.
0b1 | The GIC implementation supports two Security states.

Access to this field is RO.

#### NMI, bit [9]

Non-maskable Interrupts.

The value of this field is an IMPLEMENTATION DEFINED choice of:

NMI | Meaning
--- | ---
0b0 | Non-maskable interrupt property not supported.
0b1 | Non-maskable interrupt property is supported.

Access to this field is RO.

#### ESPI, bit [8]

Extended SPI.

The value of this field is an IMPLEMENTATION DEFINED choice of:

ESPI | Meaning
--- | ---
0b0 | Extended SPI range not implemented.
0b1 | Extended SPI range implemented.

Access to this field is RO.

#### CPUNumber, bits [7:5]

Reports the number of PEs that can be used when affinity routing is not enabled, minus 1.

These PEs must be numbered contiguously from zero, but the relationship between this number and the affinity hierarchy from MPIDR is IMPLEMENTATION DEFINED. If the implementation does not support ARE being zero, this field is 000.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### ITLinesNumber, bits [4:0]

For the INTID range 32 to 1019, indicates the maximum SPI supported.

If the value of this field is N, the maximum SPI INTID is 32(N+1) minus 1. For example, 00011 specifies that the maximum SPI INTID is 127.

Regardless of the range of INTIDs defined by this field, interrupt IDs 1020-1023 are reserved for special purposes.

A value of 0 indicates no SPIs are supported.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### Additional information

The ITLinesNumber field only indicates the maximum number of SPIs that the GIC implementation might support. This value determines the number of instances of the following interrupt registers:

- GICD_IGROUPR<n>.
- GICD_ISENABLER<n>.
- GICD_ICENABLER<n>.
- GICD_ISPENDR<n>.
- GICD_ICPENDR<n>.
- GICD_ISACTIVER<n>.
- GICD_ICACTIVER<n>.
- GICD_IPRIORITYR<n>.
- GICD_ITARGETSR<n>.
- GICD_ICFGR<n>.
- GICD_IROUTER<n>.
- GICD_IGRPMODR<n>.

The GIC architecture does not require a GIC implementation to support a continuous range of SPI interrupt IDs. Software must check which SPI INTIDs are supported, up to the maximum value indicated by GICD_TYPER.ITLinesNumber.

## Accessing GICD_TYPER

#### GICD_TYPER can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
GIC Distributor | Dist_base | 0x0004 | GICD_TYPER

Accesses on this interface are RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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