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## SCVTF (scalar, integer)

Signed integer Convert to Floating-point (scalar). This instruction converts the signed integer value in the general-purpose source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
sf | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ftype | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Rn | Rd
|  | S |  |  |  | rmode | opcode |  |  |

#### 32-bit to half-precision (sf == 0 && ftype == 11)
(FEAT_FP16)

SCVTF <Hd>, <Wn>

#### 32-bit to single-precision (sf == 0 && ftype == 00)

SCVTF <Sd>, <Wn>

#### 32-bit to double-precision (sf == 0 && ftype == 01)

SCVTF <Dd>, <Wn>

#### 64-bit to half-precision (sf == 1 && ftype == 11)
(FEAT_FP16)

SCVTF <Hd>, <Xn>

#### 64-bit to single-precision (sf == 1 && ftype == 00)

SCVTF <Sd>, <Xn>

#### 64-bit to double-precision (sf == 1 && ftype == 01)

SCVTF <Dd>, <Xn>

if ftype == '10' || (ftype == '11' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); constant integer intsize = 32 << UInt(sf); constant integer decode_fltsize = 8 << UInt(ftype EOR '10'); boolean unsigned = FALSE;

### Assembler Symbols

<Hd> | Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Wn> | Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.

<Sd> | Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Dd> | Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Xn> | Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.

### Operation

CheckFPEnabled64(); constant integer fltsize = if IsMerging(FPCR) then 128 else decode_fltsize; bits(intsize) intval = X[n, intsize]; FPRounding rounding = FPRoundingMode(FPCR); integer fracbits = 0; bits(fltsize) fltval = if IsMerging(FPCR) then V[d, fltsize] else Zeros(fltsize); Elem[fltval, 0, decode_fltsize] = FixedToFP(intval, fracbits, unsigned, FPCR, rounding, decode_fltsize); V[d, fltsize] = fltval;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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