Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## LD1RH

Load and broadcast unsigned halfword to vector

Load a single unsigned halfword from a memory address generated by a 64-bit scalar base address plus an immediate offset which is a multiple of 2 in the range 0 to 126.

Broadcast the loaded data into all active elements of the destination vector, setting the inactive elements to zero. If all elements are inactive then the instruction will not perform a read from Device memory or cause a data abort.

It has encodings from 3 classes: 16-bit element , 32-bit element and 64-bit element

### 16-bit element

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | imm6 | 1 | 0 | 1 | Pg | Rn | Zt
| dtypeh<1> | dtypeh<0> |  |  |  | dtypel<1> | dtypel<0> |  |  |

####

LD1RH { <Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

if !HaveSVE() && !HaveSME() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer g = UInt(Pg); constant integer esize = 16; constant integer msize = 16; boolean unsigned = TRUE; integer offset = UInt(imm6);

### 32-bit element

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | imm6 | 1 | 1 | 0 | Pg | Rn | Zt
| dtypeh<1> | dtypeh<0> |  |  |  | dtypel<1> | dtypel<0> |  |  |

####

LD1RH { <Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

if !HaveSVE() && !HaveSME() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer g = UInt(Pg); constant integer esize = 32; constant integer msize = 16; boolean unsigned = TRUE; integer offset = UInt(imm6);

### 64-bit element

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | imm6 | 1 | 1 | 1 | Pg | Rn | Zt
| dtypeh<1> | dtypeh<0> |  |  |  | dtypel<1> | dtypel<0> |  |  |

####

LD1RH { <Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

if !HaveSVE() && !HaveSME() then UNDEFINED; integer t = UInt(Zt); integer n = UInt(Rn); integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 16; boolean unsigned = TRUE; integer offset = UInt(imm6);

### Assembler Symbols

<Zt> | Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<imm> | Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 126, defaulting to 0, encoded in the "imm6" field.

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(64) base; bits(PL) mask = P[g, PL]; bits(VL) result; bits(msize) data; constant integer mbytes = msize DIV 8; boolean contiguous = TRUE; boolean nontemporal = FALSE; boolean tagchecked = n != 31; AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n, 64]; bits(64) addr = GenerateAddress(base, offset * mbytes, accdesc); data = Mem[addr, mbytes, accdesc]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then Elem[result, e, esize] = Extend(data, esize, unsigned); else Elem[result, e, esize] = Zeros(esize); Z[t, VL] = result;

### Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored when its governing predicate register contains the same value for each execution.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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