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# SCTLR2_EL3, System Control Register (EL3)

The SCTLR2_EL3 characteristics are:

## Purpose

Provides top level control of the system, including its memory system, at EL3.

## Configuration

This register is present only when FEAT_SCTLR2 is implemented. Otherwise, direct accesses to SCTLR2_EL3 are UNDEFINED.

## Attributes

SCTLR2_EL3 is a 64-bit register.

## Field descriptions

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0
RES0 | CPTM | RES0 | CPTA | RES0 | EnPACM | RES0 | EnANERR | EnADERR | RES0 | EMEC | RES0

#### Bits [63:12]

Reserved, RES0.

#### CPTM, bit [11]
When FEAT_CPA2 is implemented:

This field controls Checked Pointer Arithmetic for Multiplication at EL3.

CPTM | Meaning
--- | ---
0b0 | Pointer Arithmetic for Multiplication is not checked.
0b1 | Pointer Arithmetic for Multiplication is checked.

If the Effective value of SCTLR2_EL3.CPTA is 0, then the Effective value of this field is 0.

The reset behavior of this field is:

- On a Warm reset, when the highest implemented Exception level is EL3, this field resets to 0.

####
Otherwise:

Reserved, RES0.

#### Bit [10]

Reserved, RES0.

#### CPTA, bit [9]
When FEAT_CPA2 is implemented:

This field controls Checked Pointer Arithmetic for Addition at EL3.

CPTA | Meaning
--- | ---
0b0 | Pointer Arithmetic for Addition is not checked.
0b1 | Pointer Arithmetic for Addition is checked.

The reset behavior of this field is:

- On a Warm reset, when the highest implemented Exception level is EL3, this field resets to 0.

####
Otherwise:

Reserved, RES0.

#### Bit [8]

Reserved, RES0.

#### EnPACM, bit [7]
When FEAT_PAuth_LR is implemented:

PACM Enable at EL3. Controls the effect of a PACM instruction at EL3.

EnPACM | Meaning
--- | ---
0b0 | The effects of PACM are disabled at EL3.
0b1 | A PACM instruction at EL3 causes PSTATE.PACM to be set to 0b1.

The reset behavior of this field is:

- On a Warm reset, when the highest implemented Exception level is EL3, this field resets to 0.

####
Otherwise:

Reserved, RES0.

#### Bits [6:5]

Reserved, RES0.

#### EnANERR, bit [4]
When FEAT_ANERR is implemented:

Enable Asynchronous Normal Read Error.

EnANERR | Meaning
--- | ---
0b0 | External aborts on Normal memory reads generate synchronous Data Abort exceptions in the EL3 translation regime.
0b1 | External aborts on Normal memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL3 translation regime.

It is implementation-specific whether this field applies to memory reads generated by each of the following:

- When FEAT_SME is implemented:
  - SVE register loads when the PE is in Streaming SVE mode.
  - SME register loads.
- When FEAT_LSE is implemented, LD<op>, SWP and CAS{P} Atomic instructions that return a value to the PE.
- When FEAT_LS64_V is implemented, LD64B and ST64BV{0} instructions that return a value to the PE.
- When FEAT_THE is implemented, RCW instructions that return a value to the PE.

Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Normal memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.

If FEAT_SVE is implemented, SCTLR2_EL3.EnADERR is 0, and the access generating the External abort is due to any Active element of an SVE Non-fault vector load instruction or an Active element that is not the first Active element of an SVE First-fault vector load instruction, then no exception is generated and the External abort is reported in the FFR.

Setting this field to 0 might have a performance impact for Normal memory reads.

This field is ignored by the PE and treated as one when all of the following are true:

- FEAT_ADERR is implemented.
- ID_AA64MMFR3_EL1.ANERR reads as 0b0010.
- SCTLR2_EL3.EnADERR is 1.

The reset behavior of this field is:

- On a Warm reset, when the highest implemented Exception level is EL3, this field resets to 0.

####
Otherwise:

Reserved, RES0.

#### EnADERR, bit [3]
When FEAT_ADERR is implemented:

Enable Asynchronous Device Read Error.

EnADERR | Meaning
--- | ---
0b0 | External aborts on Device memory reads generate synchronous Data Abort exceptions in the EL3 translation regime.
0b1 | External aborts on Device memory reads generate synchronous Data Abort or asynchronous SError exceptions in the EL3 translation regime.

It is implementation-specific whether this field applies to memory reads generated by each of the following:

- SIMD&FP register loads.
- When FEAT_SVE is implemented, SVE register loads.
- When FEAT_SME is implemented, SME register loads.
- When FEAT_LSE is implemented, LD<op>, SWP and CAS{P} Atomic instructions that return a value to the PE.
- When FEAT_LS64_V is implemented, LD64B and ST64BV{0} instructions that return a value to the PE.
- When FEAT_THE is implemented, RCW instructions that return a value to the PE.

Setting this field to 0 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Device memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate.

If FEAT_SVE is implemented, SCTLR2_EL3.EnADERR is 0, and the access generating the External abort is due to any Active element of an SVE Non-fault vector load instruction or an Active element that is not the first Active element of an SVE First-fault vector load instruction, then no exception is generated and the External abort is reported in the FFR.

Setting this field to 0 might have a performance impact for Device memory reads.

This field is ignored by the PE and treated as one when all of the following are true:

- FEAT_ANERR is implemented.
- ID_AA64MMFR3_EL1.ADERR reads as 0b0010.
- SCTLR2_EL3.EnANERR is 1.

The reset behavior of this field is:

- On a Warm reset, when the highest implemented Exception level is EL3, this field resets to 0.

####
Otherwise:

Reserved, RES0.

#### Bit [2]

Reserved, RES0.

#### EMEC, bit [1]
When FEAT_MEC is implemented:

Enables MEC. When enabled, memory accesses to the Realm physical address space are associated with MECID_RL_A_EL3.

EMEC | Meaning
--- | ---
0b0 | MEC is not enabled for the Realm physical address space.
0b1 | MEC is enabled for the Realm physical address space.

This bit is permitted to be cached in a TLB.

The reset behavior of this field is:

- On a Warm reset, when the highest implemented Exception level is EL3, this field resets to 0.

####
Otherwise:

Reserved, RES0.

#### Bit [0]

Reserved, RES0.

## Accessing SCTLR2_EL3

Accesses to this register use the following encodings in the System register encoding space:

#### MRS <Xt>, SCTLR2_EL3

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b110 | 0b0001 | 0b0000 | 0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then X[t, 64] = SCTLR2_EL3;

#### MSR SCTLR2_EL3, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b110 | 0b0001 | 0b0000 | 0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3.SCTLR2_EL3 == '1' then AArch64.SystemAccessTrap(EL3, 0x18); else SCTLR2_EL3 = X[t, 64];

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26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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