Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## FMLAL (multiple vectors, FP8 to FP16)

Multi-vector 8-bit floating-point multiply-add long to half-precision

This 8-bit floating-point multiply-add long instruction widens all 8-bit floating-point elements in the two or four first and second source vectors to half-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE[3:0]) before being destructively added without intermediate rounding to the overlapping 16-bit half-precision elements of the ZA double-vector groups.

The lowest of the two consecutive vector numbers forming the double-vector group within each half of or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half or quarter the number of ZA array vectors. The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA double-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively.

This instruction is unpredicated.

It has encodings from 2 classes: Two ZA double-vectors and Four ZA double-vectors

### Two ZA double-vectors
(FEAT_SME_F8F16)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | Zm | 0 | 0 | Rv | 0 | 1 | 0 | Zn | 1 | 0 | 0 | 0 | off2

####

FMLAL ZA.H[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B }

if !IsFeatureImplemented(FEAT_SME_F8F16) then UNDEFINED; integer v = UInt('010':Rv); integer n = UInt(Zn:'0'); integer m = UInt(Zm:'0'); integer offset = UInt(off2:'0'); constant integer nreg = 2;

### Four ZA double-vectors
(FEAT_SME_F8F16)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | Zm | 0 | 1 | 0 | Rv | 0 | 1 | 0 | Zn | 0 | 1 | 0 | 0 | 0 | off2

####

FMLAL ZA.H[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B }

if !IsFeatureImplemented(FEAT_SME_F8F16) then UNDEFINED; integer v = UInt('010':Rv); integer n = UInt(Zn:'00'); integer m = UInt(Zm:'00'); integer offset = UInt(off2:'0'); constant integer nreg = 4;

### Assembler Symbols

<Wv> | Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.

<offs1> | Is the first vector select offset, encoded as "off2" field times 2.

<offs2> | Is the second vector select offset, encoded as "off2" field times 2 plus 1.

<Zn1> | For the two ZA double-vectors variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 2.
| For the four ZA double-vectors variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 4.

<Zn4> | Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" times 4 plus 3.

<Zn2> | Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" times 2 plus 1.

<Zm1> | For the two ZA double-vectors variant: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 2.
| For the four ZA double-vectors variant: is the name of the first scalable vector register of the second source multi-vector group, encoded as "Zm" times 4.

<Zm4> | Is the name of the fourth scalable vector register of the second source multi-vector group, encoded as "Zm" times 4 plus 3.

<Zm2> | Is the name of the second scalable vector register of the second source multi-vector group, encoded as "Zm" times 2 plus 1.

### Operation

CheckFPMREnabled(); CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 16; integer vectors = VL DIV 8; integer vstride = vectors DIV nreg; bits(32) vbase = X[v, 32]; integer vec = (UInt(vbase) + offset) MOD vstride; bits(VL) result; vec = vec - (vec MOD 2); for r = 0 to nreg-1 bits(VL) operand1 = Z[n+r, VL]; bits(VL) operand2 = Z[m+r, VL]; for i = 0 to 1 bits(VL) operand3 = ZAvector[vec + i, VL]; for e = 0 to elements-1 bits(8) element1 = Elem[operand1, 2 * e + i, 8]; bits(8) element2 = Elem[operand2, 2 * e + i, 8]; bits(16) element3 = Elem[operand3, e, 16]; Elem[result, e, 16] = FP8MulAddFP(element3, element1, element2, FPCR, FPMR); ZAvector[vec + i, VL] = result; vec = vec + vstride;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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