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## MOV (vector to tile, four registers)

Move four vector registers to four ZA tile slices

The instruction operates on four consecutive horizontal or vertical slices within a named ZA tile of the specified element size.

The consecutive slice numbers within the tile are selected starting from the sum of the slice index register and immediate offset, modulo the number of such elements in a vector. The immediate offset is a multiple of 4 in the range 0 to the number of elements in a 128-bit vector segment minus 4.

This instruction is unpredicated.

This is an alias of MOVA (vector to tile, four registers). This means:

- The encodings in this description are named to match the encodings of MOVA (vector to tile, four registers).
- The description of MOVA (vector to tile, four registers) gives the operational pseudocode, any constrained unpredictable behavior, and any operational information for this instruction.

It has encodings from 4 classes: 8-bit , 16-bit , 32-bit and 64-bit

### 8-bit

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | V | Rs | 0 | 0 | 1 | Zn | 0 | 0 | 0 | 0 | 0 | off2
|  | size<1> | size<0> |  |  |  |  |  |  |  |  |  |

####

MOV ZA0<HV>.B[<Ws>, <offs1>:<offs4>], { <Zn1>.B-<Zn4>.B }

is equivalent to

MOVA ZA0<HV>.B[<Ws>, <offs1>:<offs4>], { <Zn1>.B-<Zn4>.B }

and is always the preferred disassembly.

### 16-bit

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | V | Rs | 0 | 0 | 1 | Zn | 0 | 0 | 0 | 0 | 0 | ZAd | o1
|  | size<1> | size<0> |  |  |  |  |  |  |  |  |  |  |

####

MOV <ZAd><HV>.H[<Ws>, <offs1>:<offs4>], { <Zn1>.H-<Zn4>.H }

is equivalent to

MOVA <ZAd><HV>.H[<Ws>, <offs1>:<offs4>], { <Zn1>.H-<Zn4>.H }

and is always the preferred disassembly.

### 32-bit

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | V | Rs | 0 | 0 | 1 | Zn | 0 | 0 | 0 | 0 | 0 | ZAd
|  | size<1> | size<0> |  |  |  |  |  |  |  |  |  |

####

MOV <ZAd><HV>.S[<Ws>, <offs1>:<offs4>], { <Zn1>.S-<Zn4>.S }

is equivalent to

MOVA <ZAd><HV>.S[<Ws>, <offs1>:<offs4>], { <Zn1>.S-<Zn4>.S }

and is always the preferred disassembly.

### 64-bit

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | V | Rs | 0 | 0 | 1 | Zn | 0 | 0 | 0 | 0 | ZAd
|  | size<1> | size<0> |  |  |  |  |  |  |  |

####

MOV <ZAd><HV>.D[<Ws>, <offs1>:<offs4>], { <Zn1>.D-<Zn4>.D }

is equivalent to

MOVA <ZAd><HV>.D[<Ws>, <offs1>:<offs4>], { <Zn1>.D-<Zn4>.D }

and is always the preferred disassembly.

### Assembler Symbols

<ZAd> | For the 16-bit variant: is the name of the ZA tile ZA0-ZA1 to be accessed, encoded in the "ZAd" field.
| For the 32-bit variant: is the name of the ZA tile ZA0-ZA3 to be accessed, encoded in the "ZAd" field.
| For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 to be accessed, encoded in the "ZAd" field.

<HV> | Is the horizontal or vertical slice indicator, encoded in V:
V | <HV>
--- | ---
0 | H
1 | V

<Ws> | Is the 32-bit name of the slice index register W12-W15, encoded in the "Rs" field.

<offs1> | For the 8-bit variant: is the first slice index offset, encoded as "off2" field times 4.
| For the 16-bit variant: is the first slice index offset, encoded as "o1" field times 4.
| For the 32-bit and 64-bit variant: is the first slice index offset, with implicit value 0.

<offs4> | For the 8-bit variant: is the fourth slice index offset, encoded as "off2" field times 4 plus 3.
| For the 16-bit variant: is the fourth slice index offset, encoded as "o1" field times 4 plus 3.
| For the 32-bit and 64-bit variant: is the fourth slice index offset, with implicit value 3.

<Zn1> | Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 4.

<Zn4> | Is the name of the fourth scalable vector register of the source multi-vector group, encoded as "Zn" times 4 plus 3.

### Operation

The description of MOVA (vector to tile, four registers) gives the operational pseudocode for this instruction.

### Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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