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## FCCMP

Floating-point Conditional quiet Compare (scalar). This instruction compares the two SIMD&FP source register values and writes the result to the PSTATE.{N, Z, C, V} flags. If the condition does not pass then the PSTATE.{N, Z, C, V} flags are set to the flag bit specifier.

This instruction raises an Invalid Operation floating-point exception if either or both of the operands is a signaling NaN.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | ftype | 1 | Rm | cond | 0 | 1 | Rn | 0 | nzcv
|  |  |  |  |  |  |  |  |  | op |

#### Half-precision (ftype == 11)
(FEAT_FP16)

FCCMP <Hn>, <Hm>, #<nzcv>, <cond>

#### Single-precision (ftype == 00)

FCCMP <Sn>, <Sm>, #<nzcv>, <cond>

#### Double-precision (ftype == 01)

FCCMP <Dn>, <Dm>, #<nzcv>, <cond>

integer n = UInt(Rn); integer m = UInt(Rm); integer datasize; case ftype of when '00' datasize = 32; when '01' datasize = 64; when '10' UNDEFINED; when '11' if HaveFP16Ext() then datasize = 16; else UNDEFINED; bits(4) flags = nzcv;

### Assembler Symbols

<Dn> | Is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field.

<Dm> | Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

<Hn> | Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field.

<Hm> | Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

<Sn> | Is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field.

<Sm> | Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field.

<nzcv> | Is the flag bit specifier, an immediate in the range 0 to 15, giving the alternative state for the 4-bit NZCV condition flags, encoded in the "nzcv" field.

<cond> | Is one of the standard conditions, encoded in the "cond" field in the standard way.

### Operation

CheckFPEnabled64(); bits(datasize) operand1 = V[n, datasize]; bits(datasize) operand2; operand2 = V[m, datasize]; if ConditionHolds(cond) then flags = FPCompare(operand1, operand2, FALSE, FPCR[]); PSTATE.<N,Z,C,V> = flags;

### Operational information

The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==, > or unordered. If either or both of the operands is a NaN, they are unordered, and all three of (Operand1 < Operand2), (Operand1 == Operand2) and (Operand1 > Operand2) are false. An unordered comparison sets the PSTATE condition flags to N=0, Z=0, C=1, and V=1.

If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the NZCV condition flags written by this instruction might be significantly delayed.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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