Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## LD64B

Single-copy Atomic 64-byte Load derives an address from a base register value, loads eight 64-bit doublewords from a memory location, and writes them to consecutive registers, Xt to X(t+7). The data that is loaded is atomic and is required to be 64-byte aligned.

### Integer
(FEAT_LS64)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | Rn | Rt
size |  | VR |  | A | R |  | Rs | o3 | opc |  |  |

####

LD64B <Xt>, [<Xn|SP> {, #0}]

if !IsFeatureImplemented(FEAT_LS64) then UNDEFINED; if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED; integer t = UInt(Rt); integer n = UInt(Rn); boolean tagchecked = n != 31;

### Assembler Symbols

<Xt> | Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

### Operation

CheckLDST64BEnabled(); bits(512) data; bits(64) address; bits(64) value; AccessDescriptor accdesc = CreateAccDescLS64(MemOp_LOAD, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; data = MemLoad64B(address, accdesc); for i = 0 to 7 value = data<63+64*i : 64*i>; if BigEndian(accdesc.acctype) then value = BigEndianReverse(value); X[t+i, 64] = value;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.