Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## FMSUB

Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | ftype | 0 | Rm | 1 | Ra | Rn | Rd
M |  | S |  |  | o1 |  | o0 |  |  |

#### Half-precision (ftype == 11)
(FEAT_FP16)

FMSUB <Hd>, <Hn>, <Hm>, <Ha>

#### Single-precision (ftype == 00)

FMSUB <Sd>, <Sn>, <Sm>, <Sa>

#### Double-precision (ftype == 01)

FMSUB <Dd>, <Dn>, <Dm>, <Da>

if ftype == '10' || (ftype == '11' && !IsFeatureImplemented(FEAT_FP16)) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer a = UInt(Ra); constant integer esize = 8 << UInt(ftype EOR '10');

### Assembler Symbols

<Hd> | Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Hn> | Is the 16-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.

<Hm> | Is the 16-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.

<Ha> | Is the 16-bit name of the third SIMD&FP source register holding the minuend, encoded in the "Ra" field.

<Sd> | Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Sn> | Is the 32-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.

<Sm> | Is the 32-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.

<Sa> | Is the 32-bit name of the third SIMD&FP source register holding the minuend, encoded in the "Ra" field.

<Dd> | Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Dn> | Is the 64-bit name of the first SIMD&FP source register holding the multiplicand, encoded in the "Rn" field.

<Dm> | Is the 64-bit name of the second SIMD&FP source register holding the multiplier, encoded in the "Rm" field.

<Da> | Is the 64-bit name of the third SIMD&FP source register holding the minuend, encoded in the "Ra" field.

### Operation

CheckFPEnabled64(); bits(esize) addend = V[a, esize]; bits(esize) operand1 = FPNeg(V[n, esize], FPCR); bits(esize) operand2 = V[m, esize]; bits(128) result = if IsMerging(FPCR) then V[a, 128] else Zeros(128); Elem[result, 0, esize] = FPMulAdd(addend, operand1, operand2, FPCR); V[d, 128] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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