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# GICR_ICENABLER0, Interrupt Clear-Enable Register 0

The GICR_ICENABLER0 characteristics are:

## Purpose

Disables forwarding of the corresponding SGI or PPI to the CPU interfaces.

## Configuration

A copy of this register is provided for each Redistributor.

## Attributes

GICR_ICENABLER0 is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Clear_enable_bit31 | Clear_enable_bit30 | Clear_enable_bit29 | Clear_enable_bit28 | Clear_enable_bit27 | Clear_enable_bit26 | Clear_enable_bit25 | Clear_enable_bit24 | Clear_enable_bit23 | Clear_enable_bit22 | Clear_enable_bit21 | Clear_enable_bit20 | Clear_enable_bit19 | Clear_enable_bit18 | Clear_enable_bit17 | Clear_enable_bit16 | Clear_enable_bit15 | Clear_enable_bit14 | Clear_enable_bit13 | Clear_enable_bit12 | Clear_enable_bit11 | Clear_enable_bit10 | Clear_enable_bit9 | Clear_enable_bit8 | Clear_enable_bit7 | Clear_enable_bit6 | Clear_enable_bit5 | Clear_enable_bit4 | Clear_enable_bit3 | Clear_enable_bit2 | Clear_enable_bit1 | Clear_enable_bit0

#### Clear_enable_bit<x>, bit [x], for x = 31 to 0

For PPIs and SGIs, controls the forwarding of interrupt number x to the CPU interfaces. Reads and writes have the following behavior:

Clear_enable_bit<x> | Meaning
--- | ---
0b0 | If read, indicates that forwarding of the corresponding interrupt is disabled. If written, has no effect.
0b1 | If read, indicates that forwarding of the corresponding interrupt is enabled. If written, disables forwarding of the corresponding interrupt. After a write of 1 to this bit, a subsequent read of this bit returns 0.

The reset behavior of this field is:

- On a GIC reset, this field resets to an architecturally UNKNOWN value.

## Accessing GICR_ICENABLER0

When affinity routing is not enabled for the Security state of an interrupt in GICR_ICENABLER0, the corresponding bit is RAZ/WI and equivalent functionality is provided by GICD_ICENABLER<n> with n=0.

This register only applies to SGIs (bits [15:0]) and PPIs (bits [31:16]). For SPIs, this functionality is provided by GICD_ICENABLER<n>.

When GICD_CTLR.DS == 0, bits corresponding to Secure SGIs and PPIs are RAZ/WI to Non-secure accesses.

#### GICR_ICENABLER0 can be accessed through the memory-mapped interfaces:

Component | Frame | Offset | Instance
--- | --- | --- | ---
GIC Redistributor | SGI_base | 0x0180 | GICR_ICENABLER0

Accesses on this interface are RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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