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# DCZID_EL0, Data Cache Zero ID Register

The DCZID_EL0 characteristics are:

## Purpose

Indicates the block size that is written with byte values of 0 by the DC ZVA (Data Cache Zero by Address) System instruction.

If FEAT_MTE is implemented, this register also indicates the granularity at which the DC GVA and DC GZVA instructions write.

## Configuration

There are no configuration notes.

## Attributes

DCZID_EL0 is a 64-bit register.

## Field descriptions

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0
RES0 | DZP | BS

#### Bits [63:5]

Reserved, RES0.

#### DZP, bit [4]

Data Zero Prohibited. This field indicates whether use of DC ZVA instructions is permitted or prohibited.

If FEAT_MTE is implemented, this field also indicates whether use of the DC GVA and DC GZVA instructions are permitted or prohibited.

DZP | Meaning
--- | ---
0b0 | Instructions are permitted.
0b1 | Instructions are prohibited.

The value read from this field is governed by the current Exception level and the values of the following fields:

- The Effective value of HCR_EL2.TDZ.

- When the Effective value of HCR_EL2.{E2H, TGE} != '11', SCTLR_EL1.DZE.

- When the Effective value of HCR_EL2.{E2H, TGE} == '11', SCTLR_EL2.DZE.

#### BS, bits [3:0]

Log2 of the block size in words. The maximum size supported is 2KB, indicated by value 0b1001.

If FEAT_MTE2 is implemented, the minimum size supported is 16 bytes, indicated by value 0b0010.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

## Accessing DCZID_EL0

Accesses to this register use the following encodings in the System register encoding space:

#### MRS <Xt>, DCZID_EL0

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b11 | 0b011 | 0b0000 | 0b0000 | 0b111

if PSTATE.EL == EL0 then if EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.DCZID_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = DCZID_EL0; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.DCZID_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = DCZID_EL0; elsif PSTATE.EL == EL2 then X[t, 64] = DCZID_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = DCZID_EL0;

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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