Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## LDR (table)

Load ZT0 register

Load the 64-byte ZT0 register from the memory address provided in the 64-bit scalar base register. This instruction is unpredicated.

The load is performed as contiguous byte accesses, with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then the base register must be aligned to 16 bytes.

This instruction does not require the PE to be in Streaming SVE mode, and it is expected that this instruction will not experience a significant slowdown due to contention with other PEs that are executing in Streaming SVE mode.

### SME2
(FEAT_SME2)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | Rn | 0 | 0 | 0 | 0 | 0

####

LDR ZT0, [<Xn|SP>]

if !HaveSME2() then UNDEFINED; integer n = UInt(Rn);

### Assembler Symbols

<Xn|SP> | Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

### Operation

CheckSMEEnabled(); CheckSMEZT0Enabled(); constant integer elements = 512 DIV 8; bits(64) base; bits(512) result; boolean contiguous = TRUE; boolean nontemporal = FALSE; boolean tagchecked = n != 31; AccessDescriptor accdesc = CreateAccDescSME(MemOp_LOAD, nontemporal, contiguous, tagchecked); if HaveTME() && TSTATE.depth > 0 then FailTransaction(TMFailure_ERR, FALSE); if n == 31 then CheckSPAlignment(); base = SP[]; else base = X[n, 64]; boolean aligned = IsAligned(base, 16); if !aligned && AlignmentEnforced() then AArch64.Abort(base, AlignmentFault(accdesc)); for e = 0 to elements-1 Elem[result, e, 8] = AArch64.MemSingle[base + e, 1, accdesc, aligned]; ZT0[512] = result;

### Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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