Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## PRFH (vector plus immediate)

Gather prefetch halfwords (vector plus immediate)

Gather prefetch of halfwords from the active memory addresses generated by a vector base plus immediate index. The index is a multiple of 2 in the range 0 to 62. Inactive addresses are not prefetched from memory.

The <prfop> symbol specifies the prefetch hint as a combination of three options: access type PLD for load or PST for store; target cache level L1, L2 or L3; temporality (KEEP for temporal or STRM for non-temporal).

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

It has encodings from 2 classes: 32-bit element and 64-bit element

### 32-bit element

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | imm5 | 1 | 1 | 1 | Pg | Zn | 0 | prfop
| msz<1> | msz<0> |  |  |  |  |  |  |

####

PRFH <prfop>, <Pg>, [<Zn>.S{, #<imm>}]

if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer esize = 32; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer level = UInt(prfop<2:1>); constant boolean stream = (prfop<0> == '1'); constant PrefetchHint pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE; constant integer scale = 1; constant integer offset = UInt(imm5);

### 64-bit element

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | imm5 | 1 | 1 | 1 | Pg | Zn | 0 | prfop
| msz<1> | msz<0> |  |  |  |  |  |  |

####

PRFH <prfop>, <Pg>, [<Zn>.D{, #<imm>}]

if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer level = UInt(prfop<2:1>); constant boolean stream = (prfop<0> == '1'); constant PrefetchHint pref_hint = if prfop<3> == '0' then Prefetch_READ else Prefetch_WRITE; constant integer scale = 1; constant integer offset = UInt(imm5);

### Assembler Symbols

<prfop> | Is the prefetch operation specifier, encoded in prfop:
prfop | <prfop>
--- | ---
0000 | PLDL1KEEP
0001 | PLDL1STRM
0010 | PLDL2KEEP
0011 | PLDL2STRM
0100 | PLDL3KEEP
0101 | PLDL3STRM
x11x | #uimm4
1000 | PSTL1KEEP
1001 | PSTL1STRM
1010 | PSTL2KEEP
1011 | PSTL2STRM
1100 | PSTL3KEEP
1101 | PSTL3STRM

<Pg> | Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn> | Is the name of the base scalable vector register, encoded in the "Zn" field.

<imm> | Is the optional unsigned immediate byte offset, a multiple of 2 in the range 0 to 62, defaulting to 0, encoded in the "imm5" field.

### Operation

CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; bits(VL) base; if AnyActiveElement(mask, esize) then base = Z[n, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant bits(64) addr = ZeroExtend(Elem[base, e, esize], 64) + (offset << scale); Hint_Prefetch(addr, pref_hint, level, stream);

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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