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## DSB

Data Synchronization Barrier is a memory barrier that ensures the completion of memory accesses, see Data Synchronization Barrier.

A DSB instruction with the nXS qualifier is complete when the subset of these memory accesses with the XS attribute set to 0 are complete. It does not require that memory accesses with the XS attribute set to 1 are complete.

This instruction is used by the aliases PSSBB, and SSBB.

It has encodings from 2 classes: Memory barrier and Memory nXS barrier

### Memory barrier

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | CRm | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1
|  |  |  |  |  |  | opc |

####

DSB <option>|#<imm>

boolean nXS = FALSE; DSBAlias alias; case CRm of when '0000' alias = DSBAlias_SSBB; when '0100' alias = DSBAlias_PSSBB; otherwise alias = DSBAlias_DSB; MBReqDomain domain; case CRm<3:2> of when '00' domain = MBReqDomain_OuterShareable; when '01' domain = MBReqDomain_Nonshareable; when '10' domain = MBReqDomain_InnerShareable; when '11' domain = MBReqDomain_FullSystem; MBReqTypes types; case CRm<1:0> of when '00' types = MBReqTypes_All; domain = MBReqDomain_FullSystem; when '01' types = MBReqTypes_Reads; when '10' types = MBReqTypes_Writes; when '11' types = MBReqTypes_All;

### Memory nXS barrier
(FEAT_XS)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | imm2 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1

####

DSB <option>nXS

if !HaveFeatXS() then UNDEFINED; MBReqTypes types = MBReqTypes_All; boolean nXS = TRUE; DSBAlias alias = DSBAlias_DSB; MBReqDomain domain; case imm2 of when '00' domain = MBReqDomain_OuterShareable; when '01' domain = MBReqDomain_Nonshareable; when '10' domain = MBReqDomain_InnerShareable; when '11' domain = MBReqDomain_FullSystem;

### Assembler Symbols

<option> | For the memory barrier variant: specifies the limitation on the barrier operation. Values are: SY Full system is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. This option is referred to as the full system barrier. Encoded as CRm = 0b1111. ST Full system is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as CRm = 0b1110. LD Full system is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as CRm = 0b1101. ISH Inner Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as CRm = 0b1011. ISHST Inner Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as CRm = 0b1010. ISHLD Inner Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as CRm = 0b1001. NSH Non-shareable is the required shareability domain, reads and writes are the required access, both before and after the barrier instruction. Encoded as CRm = 0b0111. NSHST Non-shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as CRm = 0b0110. NSHLD Non-shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as CRm = 0b0101. OSH Outer Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as CRm = 0b0011. OSHST Outer Shareable is the required shareability domain, writes are the required access type, both before and after the barrier instruction. Encoded as CRm = 0b0010. OSHLD Outer Shareable is the required shareability domain, reads are the required access type before the barrier instruction, and reads and writes are the required access types after the barrier instruction. Encoded as CRm = 0b0001. All other encodings of "CRm", other than the values 0b0000 and 0b0100, that are not listed above are reserved, and can be encoded using the #<imm> syntax. All unsupported and reserved options must execute as a full system barrier operation, but software must not rely on this behavior. For more information on whether an access is before or after a barrier instruction, see Data Memory Barrier (DMB) or see Data Synchronization Barrier (DSB). #### Note The value 0b0000 is used to encode SSBB and the value 0b0100 is used to encode PSSBB.
| For the memory nXS barrier variant: specifies the limitation on the barrier operation. Values are: SY Full system is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. This option is referred to as the full system barrier. Encoded as imm2 = 0b11. ISH Inner Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as imm2 = 0b10. NSH Non-shareable is the required shareability domain, reads and writes are the required access, both before and after the barrier instruction. Encoded as imm2 = 0b01. OSH Outer Shareable is the required shareability domain, reads and writes are the required access types, both before and after the barrier instruction. Encoded as imm2 = 0b00.

<imm> | Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "CRm" field.

### Alias Conditions

Alias | Is preferred when
--- | ---
PSSBB | CRm == '0100'
SSBB | CRm == '0000'

### Operation

case alias of when DSBAlias_SSBB SpeculativeStoreBypassBarrierToVA(); when DSBAlias_PSSBB SpeculativeStoreBypassBarrierToPA(); when DSBAlias_DSB if HaveTME() && TSTATE.depth > 0 then FailTransaction(TMFailure_ERR, FALSE); if !nXS && HaveFeatXS() then nXS = PSTATE.EL IN {EL0, EL1} && IsHCRXEL2Enabled() && HCRX_EL2.FnXS == '1'; DataSynchronizationBarrier(domain, types, nXS); otherwise Unreachable();

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.64, AdvSIMD v29.12, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T19:42

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