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# AMCNTENSET, Activity Monitors Count Enable Set Register

The AMCNTENSET characteristics are:

## Purpose

Enable control bits for the architected and auxiliary activity monitors event counters, AMEVCNTR0<n> and AMEVCNTR1<n>.

## Configuration

External register AMCNTENSET bits [31:0] are architecturally mapped to AArch64 System register AMCNTENSET0_EL0[31:0].

External register AMCNTENSET bits [63:32] are architecturally mapped to AArch64 System register AMCNTENSET1_EL0[31:0].

It is IMPLEMENTATION DEFINED whether AMCNTENSET is implemented in the Core power domain or in the Debug power domain.

This register is present only when FEAT_AMUv1 is implemented and FEAT_AMU_EXT64 is implemented. Otherwise, direct accesses to AMCNTENSET are RES0.

## Attributes

AMCNTENSET is a 64-bit register.

This register is part of the AMU block.

## Field descriptions

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | P115 | P114 | P113 | P112 | P111 | P110 | P19 | P18 | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10
RES0 | RAZ/WI | P03 | P02 | P01 | P00

#### Bits [63:48]

Reserved, RES0.

#### P1<n>, bit [n+32], for n = 15 to 0

Activity monitor event counter enable bit for AMEVCNTR1<n>.

When N is less than 16, bits [15:N] are RAZ, where N is the value in AMCGCR.CG1NC.

Possible values of each bit are:

P1<n> | Meaning
--- | ---
0b0 | When read, means that AMEVCNTR1<n> is disabled.
0b1 | When read, means that AMEVCNTR1<n> is enabled.

The reset behavior of this field is:

- On an AMU reset, this field resets to 0.

#### Bits [31:16]

Reserved, RES0.

#### Bits [15:4]

Reserved, RAZ/WI.

This field is reserved for additional architected activity monitor event counters, which Arm might define in a future version of the Activity Monitors architecture.

#### P0<n>, bit [n], for n = 3 to 0

Activity monitor event counter enable bit for AMEVCNTR0<n>.

Note

AMCGCR.CG0NC identifies the number of architected activity monitor event counters. In an implementation that includes FEAT_AMUv1, the number of architected activity monitor event counters is 4.

Possible values of each bit are:

P0<n> | Meaning
--- | ---
0b0 | When read, means that AMEVCNTR0<n> is disabled.
0b1 | When read, means that AMEVCNTR0<n> is enabled.

The reset behavior of this field is:

- On an AMU reset, this field resets to 0.

## Accessing AMCNTENSET

If there are no auxiliary monitor event counters implemented, reads of AMCNTENSET[63:32] are RAZ. Software must treat reserved accesses as RES0. See 'Access requirements for reserved and unallocated registers'.

Note

There are no implemented auxiliary activity monitor event counters when AMCFGR.NCG == 0b0000.

Accesses to this register use the following encodings:

Accessible at offset 0xC00 from AMU

Accesses on this interface are RO.

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26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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