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# IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable

The IC IALLUIS characteristics are:

## Purpose

Invalidate all instruction caches in the Inner Shareable domain of the PE executing the instruction to the Point of Unification.

## Configuration

AArch64 System instruction IC IALLUIS performs the same function as AArch32 System instruction ICIALLUIS.

## Attributes

IC IALLUIS is a 64-bit System instruction.

## Field descriptions

This instruction has no applicable fields.

The value in the register specified by <Xt> is ignored.

## Executing IC IALLUIS

The Rt field should be set to 0b11111. If the Rt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether:

- The instruction is UNDEFINED.

- The instruction behaves as if the Rt field is set to 0b11111.

Accesses to this instruction use the following encodings in the System instruction encoding space:

#### IC IALLUIS{, <Xt>}

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b01 | 0b000 | 0b0111 | 0b0001 | 0b000

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TPU == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.TICAB == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGITR_EL2.ICIALLUIS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.IC(CacheOpScope_ALLUIS); elsif PSTATE.EL == EL2 then AArch64.IC(CacheOpScope_ALLUIS); elsif PSTATE.EL == EL3 then AArch64.IC(CacheOpScope_ALLUIS);

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26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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