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# TRCSTATR, Trace Status Register

The TRCSTATR characteristics are:

## Purpose

Returns the trace unit status.

## Configuration

External register TRCSTATR bits [31:0] are architecturally mapped to AArch64 System register TRCSTATR[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCSTATR are RES0.

## Attributes

TRCSTATR is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | PMSTABLE | IDLE

#### Bits [31:2]

Reserved, RES0.

#### PMSTABLE, bit [1]

Programmers' model stable.

PMSTABLE | Meaning
--- | ---
0b0 | The programmers' model is not stable.
0b1 | The programmers' model is stable.

Accessing this field has the following behavior:

- When the trace unit is enabled, access to this field is UNKNOWN/WI.
- Otherwise, access to this field is RO.

#### IDLE, bit [0]

Idle status.

IDLE | Meaning
--- | ---
0b0 | The trace unit is not idle.
0b1 | The trace unit is idle.

## Accessing TRCSTATR

#### TRCSTATR can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
ETE | 0x00C | TRCSTATR

This interface is accessible as follows:

- When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered(), accesses to this register generate an error response.
- Otherwise, accesses to this register are RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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