Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## INS (general)

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

This instruction is used by the alias MOV (from general).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | 0 | 0 | 1 | 1 | 1 | Rn | Rd
| Q | op |  |  |  | imm4 |  |  |

####

INS <Vd>.<Ts>[<index>], <R><n>

integer d = UInt(Rd); integer n = UInt(Rn); constant integer size = LowestSetBit(imm5); if size > 3 then UNDEFINED; constant integer index = UInt(imm5<4:size+1>); constant integer esize = 8 << size;

### Assembler Symbols

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ts> | Is an element size specifier, encoded in imm5:
imm5 | <Ts>
--- | ---
x0000 | RESERVED
xxxx1 | B
xxx10 | H
xx100 | S
x1000 | D

<index> | Is the element index encoded in imm5:
imm5 | <index>
--- | ---
x0000 | RESERVED
xxxx1 | UInt(imm5<4:1>)
xxx10 | UInt(imm5<4:2>)
xx100 | UInt(imm5<4:3>)
x1000 | UInt(imm5<4>)

<R> | Is the width specifier for the general-purpose source register, encoded in imm5:
imm5 | <R>
--- | ---
x0000 | RESERVED
xxxx1 | W
xxx10 | W
xx100 | W
x1000 | X

<n> | Is the number [0-30] of the general-purpose source register or ZR (31), encoded in the "Rn" field.

### Operation

CheckFPAdvSIMDEnabled64(); bits(esize) element = X[n, esize]; bits(128) result; result = V[d, 128]; Elem[result, index, esize] = element; V[d, 128] = result;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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