Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## BIC (vector, immediate)

Bitwise bit Clear (vector, immediate). This instruction reads each vector element from the destination SIMD&FP register, performs a bitwise AND between each result and the complement of an immediate constant, places the result into a vector, and writes the vector to the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | a | b | c | x | x | x | 1 | 0 | 1 | d | e | f | g | h | Rd
|  | op |  |  |  |  | cmode |  |  |  |  |  |  |  |

#### 16-bit (cmode == 10x1)

BIC <Vd>.<T>, #<imm8>{, LSL #<amount>}

#### 32-bit (cmode == 0xx1)

BIC <Vd>.<T>, #<imm8>{, LSL #<amount>}

integer rd = UInt(Rd); integer datasize = if Q == '1' then 128 else 64; bits(datasize) imm; bits(64) imm64; ImmediateOp operation; case cmode:op of when '0xx01' operation = ImmediateOp_MVNI; when '0xx11' operation = ImmediateOp_BIC; when '10x01' operation = ImmediateOp_MVNI; when '10x11' operation = ImmediateOp_BIC; when '110x1' operation = ImmediateOp_MVNI; when '1110x' operation = ImmediateOp_MOVI; when '11111' // FMOV Dn,#imm is in main FP instruction set if Q == '0' then UNDEFINED; operation = ImmediateOp_MOVI; imm64 = AdvSIMDExpandImm(op, cmode, a:b:c:d:e:f:g:h); imm = Replicate(imm64, datasize DIV 64);

### Assembler Symbols

<Vd> | Is the name of the SIMD&FP register, encoded in the "Rd" field.

<T> | For the 16-bit variant: is an arrangement specifier, encoded in Q:
Q | <T>
--- | ---
0 | 4H
1 | 8H
| For the 32-bit variant: is an arrangement specifier, encoded in Q:
Q | <T>
--- | ---
0 | 2S
1 | 4S

<imm8> | Is an 8-bit immediate encoded in "a:b:c:d:e:f:g:h".

<amount> | For the 16-bit variant: is the shift amount encoded in cmode<1>:
cmode<1> | <amount>
--- | ---
0 | 0
1 | 8
defaulting to 0 if LSL is omitted.
| For the 32-bit variant: is the shift amount encoded in cmode<2:1>:
cmode<2:1> | <amount>
--- | ---
00 | 0
01 | 8
10 | 16
11 | 24
defaulting to 0 if LSL is omitted.

### Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand; bits(datasize) result; case operation of when ImmediateOp_MOVI result = imm; when ImmediateOp_MVNI result = NOT(imm); when ImmediateOp_ORR operand = V[rd, datasize]; result = operand OR imm; when ImmediateOp_BIC operand = V[rd, datasize]; result = operand AND NOT(imm); V[rd, datasize] = result;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.64, AdvSIMD v29.12, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T19:42

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