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# GITS_CREADR, ITS Read Register

The GITS_CREADR characteristics are:

## Purpose

Specifies the offset from GITS_CBASER where the ITS reads the next ITS command.

## Configuration

This register is cleared to 0 when a value is written to GITS_CBASER.

Bits [63:32] and bits [31:0] are accessible separately.

## Attributes

GITS_CREADR is a 64-bit register.

## Field descriptions

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0
RES0 | Offset | RES0 | Stalled

#### Bits [63:20]

Reserved, RES0.

#### Offset, bits [19:5]

Bits [19:5] of the offset from GITS_CBASER. Bits [4:0] of the offset are zero.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

#### Bits [4:1]

Reserved, RES0.

#### Stalled, bit [0]

Reports whether the processing of commands is stalled because of a command error.

Stalled | Meaning
--- | ---
0b0 | ITS command queue is not stalled because of a command error.
0b1 | ITS command queue is stalled because of a command error.

#### Additional information

For more information, see 'The ITS command interface' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).

## Accessing GITS_CREADR

#### GITS_CREADR can be accessed through the memory-mapped interfaces:

Component | Offset | Instance
--- | --- | ---
GIC ITS control | 0x0090 | GITS_CREADR

Accesses on this interface are RO.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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