Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## BRB

Branch Record Buffer. For more information, see op0==0b01, cache maintenance, TLB maintenance, and address translation instructions.

This is an alias of SYS. This means:

- The encodings in this description are named to match the encodings of SYS.
- The description of SYS gives the operational pseudocode, any constrained unpredictable behavior, and any operational information for this instruction.

### System
(FEAT_BRBE)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | op2 | Rt
| L |  | op1 | CRn | CRm |  |

####

BRB <brb_op>{, <Xt>}

is equivalent to

SYS #1, C7, C2, #<op2>{, <Xt>}

and is the preferred disassembly when SysOp('001','0111','0010',op2) == Sys_BRB.

### Assembler Symbols

<brb_op> | Is a BRB instruction name, as listed for the BRB system instruction group, encoded in op2:
op2 | <brb_op> | Architectural Feature
--- | --- | ---
100 | IALL | FEAT_BRBE
101 | INJ | FEAT_BRBE

<op2> | Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.

<Xt> | Is the 64-bit name of the optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field.

### Operation

The description of SYS gives the operational pseudocode for this instruction.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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