Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## UBFM

Unsigned Bitfield Move is usually accessed via one of its aliases, which are always preferred for disassembly.

If <imms> is greater than or equal to <immr>, this copies a bitfield of (<imms>-<immr>+1) bits starting from bit position <immr> in the source register to the least significant bits of the destination register.

If <imms> is less than <immr>, this copies a bitfield of (<imms>+1) bits from the least significant bits of the source register to bit position (regsize-<immr>) of the destination register, where regsize is the destination register size of 32 or 64 bits.

In both cases the destination bits below and above the bitfield are set to zero.

This instruction is used by the aliases LSL (immediate), LSR (immediate), UBFIZ, UBFX, UXTB, and UXTH.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
sf | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | N | immr | imms | Rn | Rd
| opc |  |  |  |  |  |

#### 32-bit (sf == 0 && N == 0)

UBFM <Wd>, <Wn>, #<immr>, #<imms>

#### 64-bit (sf == 1 && N == 1)

UBFM <Xd>, <Xn>, #<immr>, #<imms>

integer d = UInt(Rd); integer n = UInt(Rn); integer datasize = if sf == '1' then 64 else 32; integer r; bits(datasize) wmask; bits(datasize) tmask; if sf == '1' && N != '1' then UNDEFINED; if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then UNDEFINED; r = UInt(immr); (wmask, tmask) = DecodeBitMasks(N, imms, immr, FALSE, datasize);

### Assembler Symbols

<Wd> | Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wn> | Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.

<Xd> | Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xn> | Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.

<immr> | For the 32-bit variant: is the right rotate amount, in the range 0 to 31, encoded in the "immr" field.
| For the 64-bit variant: is the right rotate amount, in the range 0 to 63, encoded in the "immr" field.

<imms> | For the 32-bit variant: is the leftmost bit number to be moved from the source, in the range 0 to 31, encoded in the "imms" field.
| For the 64-bit variant: is the leftmost bit number to be moved from the source, in the range 0 to 63, encoded in the "imms" field.

### Alias Conditions

Alias | Of variant | Is preferred when
--- | --- | ---
LSL (immediate) | 32-bit | imms != '011111' && imms + 1 == immr
LSL (immediate) | 64-bit | imms != '111111' && imms + 1 == immr
LSR (immediate) | 32-bit | imms == '011111'
LSR (immediate) | 64-bit | imms == '111111'
UBFIZ |  | UInt(imms) < UInt(immr)
UBFX |  | BFXPreferred(sf, opc<1>, imms, immr)
UXTB |  | immr == '000000' && imms == '000111'
UXTH |  | immr == '000000' && imms == '001111'

### Operation

bits(datasize) src = X[n, datasize]; // perform bitfield move on low bits bits(datasize) bot = ROR(src, r) AND wmask; // combine extension bits and result bits X[d, datasize] = bot AND tmask;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.