Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## SHA1SU1

SHA1 schedule update 1.

### Advanced SIMD
(FEAT_SHA1)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | Rn | Rd

####

SHA1SU1 <Vd>.4S, <Vn>.4S

integer d = UInt(Rd); integer n = UInt(Rn); if !HaveSHA1Ext() then UNDEFINED;

### Assembler Symbols

<Vd> | Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.

<Vn> | Is the name of the second SIMD&FP source register, encoded in the "Rn" field.

### Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(128) operand1 = V[d, 128]; bits(128) operand2 = V[n, 128]; bits(128) result; bits(128) T = operand1 EOR LSR(operand2, 32); result<31:0> = ROL(T<31:0>, 1); result<63:32> = ROL(T<63:32>, 1); result<95:64> = ROL(T<95:64>, 1); result<127:96> = ROL(T<127:96>, 1) EOR ROL(T<31:0>, 2); V[d, 128] = result;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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