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## FMLALL (multiple and indexed vector)

Multi-vector 8-bit floating-point multiply-add long-long by indexed element to single-precision

This 8-bit floating-point multiply-add long long instruction widens all 8-bit floating-point elements in the one, two, or four first source vectors and the indexed element of the second source vector to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE) before being destructively added without intermediate rounding to the overlapping 32-bit single-precision elements of the ZA quad-vector groups.

The 8-bit floating-point elements within the second source vector are specified using a 4-bit immediate index which selects the same element position within each 128-bit vector segment.

The quad-vector group within all of, each half of, or each quarter of the ZA array is selected by the sum of the vector select register and offset range, modulo all, half, or quarter the number of ZA array vectors.

The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA quad-vector groups respectively. The vector group symbol is preferred for disassembly, but optional in assembler source code.

The 8-bit floating-point encoding format for the elements of the first source vector and the second source vector is selected by FPMR.F8S1 and FPMR.F8S2 respectively.

This instruction is unpredicated.

It has encodings from 3 classes: One ZA quad-vector , Two ZA quad-vectors and Four ZA quad-vectors

### One ZA quad-vector
(FEAT_SME_F8F32)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | Zm | i4h | Rv | i4l | Zn | 0 | 0 | 0 | off2

####

FMLALL ZA.S[<Wv>, <offs1>:<offs4>], <Zn>.B, <Zm>.B[<index>]

if !IsFeatureImplemented(FEAT_SME_F8F32) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer n = UInt(Zn); constant integer m = UInt('0':Zm); constant integer offset = UInt(off2:'00'); constant integer index = UInt(i4h:i4l); constant integer nreg = 1;

### Two ZA quad-vectors
(FEAT_SME_F8F32)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | Zm | 0 | Rv | 0 | i4h | Zn | 1 | 0 | 0 | i4l | o1

####

FMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>]

if !IsFeatureImplemented(FEAT_SME_F8F32) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer n = UInt(Zn:'0'); constant integer m = UInt('0':Zm); constant integer offset = UInt(o1:'00'); constant integer index = UInt(i4h:i4l); constant integer nreg = 2;

### Four ZA quad-vectors
(FEAT_SME_F8F32)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | Zm | 1 | Rv | 0 | i4h | Zn | 1 | 0 | 0 | 0 | i4l | o1

####

FMLALL ZA.S[<Wv>, <offs1>:<offs4>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>]

if !IsFeatureImplemented(FEAT_SME_F8F32) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer n = UInt(Zn:'00'); constant integer m = UInt('0':Zm); constant integer offset = UInt(o1:'00'); constant integer index = UInt(i4h:i4l); constant integer nreg = 4;

### Assembler Symbols

<Wv> | Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.

<offs1> | For the one ZA quad-vector variant: is the first vector select offset, encoded as "off2" field times 4.
| For the four ZA quad-vectors and two ZA quad-vectors variant: is the first vector select offset, encoded as "o1" field times 4.

<offs4> | For the one ZA quad-vector variant: is the fourth vector select offset, encoded as "off2" field times 4 plus 3.
| For the four ZA quad-vectors and two ZA quad-vectors variant: is the fourth vector select offset, encoded as "o1" field times 4 plus 3.

<Zn> | Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zn1> | For the two ZA quad-vectors variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 2.
| For the four ZA quad-vectors variant: is the name of the first scalable vector register of the first source multi-vector group, encoded as "Zn" times 4.

<Zn4> | Is the name of the fourth scalable vector register of the first source multi-vector group, encoded as "Zn" times 4 plus 3.

<Zn2> | Is the name of the second scalable vector register of the first source multi-vector group, encoded as "Zn" times 2 plus 1.

<Zm> | Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.

<index> | Is the element index, in the range 0 to 15, encoded in the "i4h:i4l" fields.

### Operation

CheckFPMREnabled(); CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 32; constant integer vectors = VL DIV 8; constant integer vstride = vectors DIV nreg; constant integer eltspersegment = 128 DIV 32; constant bits(32) vbase = X[v, 32]; integer vec = (UInt(vbase) + offset) MOD vstride; bits(VL) result; vec = vec - (vec MOD 4); for r = 0 to nreg-1 constant bits(VL) operand1 = Z[n+r, VL]; constant bits(VL) operand2 = Z[m, VL]; for i = 0 to 3 constant bits(VL) operand3 = ZAvector[vec + i, VL]; for e = 0 to elements-1 constant integer segmentbase = e - (e MOD eltspersegment); constant integer s = 4 * segmentbase + index; constant bits(8) element1 = Elem[operand1, 4 * e + i, 8]; constant bits(8) element2 = Elem[operand2, s, 8]; constant bits(32) element3 = Elem[operand3, e, 32]; Elem[result, e, 32] = FP8MulAddFP(element3, element1, element2, FPCR, FPMR); ZAvector[vec + i, VL] = result; vec = vec + vstride;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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