Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## USHLL, USHLL2

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

The USHLL instruction extracts vector elements from the lower half of the source register. The USHLL2 instruction extracts vector elements from the upper half of the source register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

This instruction is used by the alias UXTL, UXTL2.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 1 | 0 | 1 | 1 | 1 | 1 | 0 | != 0000 | immb | 1 | 0 | 1 | 0 | 0 | 1 | Rn | Rd
|  | U |  | immh |  | opcode |  |  |

####

USHLL{2} <Vd>.<Ta>, <Vn>.<Tb>, #<shift>

integer d = UInt(Rd); integer n = UInt(Rn); if immh == '0000' then SEE(asimdimm); if immh<3> == '1' then UNDEFINED; constant integer esize = 8 << HighestSetBit(immh); constant integer datasize = 64; integer part = UInt(Q); integer elements = datasize DIV esize; integer shift = UInt(immh:immb) - esize; boolean unsigned = (U == '1');

### Assembler Symbols

2 | Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is encoded in Q:
Q | 2
--- | ---
0 | [absent]
1 | [present]

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta> | Is an arrangement specifier, encoded in immh:
immh | <Ta>
--- | ---
0001 | 8H
001x | 4S
01xx | 2D
1xxx | RESERVED

<Vn> | Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<Tb> | Is an arrangement specifier, encoded in immh:Q:
immh | Q | <Tb>
--- | --- | ---
0001 | 0 | 8B
0001 | 1 | 16B
001x | 0 | 4H
001x | 1 | 8H
01xx | 0 | 2S
01xx | 1 | 4S
1xxx | x | RESERVED

<shift> | Is the left shift amount, in the range 0 to the source element width in bits minus 1, encoded in immh:immb:
immh | <shift>
--- | ---
0001 | UInt(immh:immb) - 8
001x | UInt(immh:immb) - 16
01xx | UInt(immh:immb) - 32
1xxx | RESERVED

### Alias Conditions

Alias | Is preferred when
--- | ---
UXTL, UXTL2 | immb == '000' && BitCount(immh) == 1

### Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = Vpart[n, part, datasize]; bits(datasize*2) result; integer element; for e = 0 to elements-1 element = Int(Elem[operand, e, esize], unsigned) << shift; Elem[result, e, 2*esize] = element<2*esize-1:0>; V[d, datasize*2] = result;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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