Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## BF1CVTLT, BF2CVTLT

8-bit floating-point convert to BFloat16 (top)

Convert each odd-numbered 8-bit floating-point element of the source vector to BFloat16 while downscaling the value, and place the results in the overlapping 16-bit elements of the destination vector. BF1CVTLT scales the values by 2-UInt(FPMR.LSCALE[5:0]). BF2CVTLT scales the values by 2-UInt(FPMR.LSCALE2[5:0]).

The 8-bit floating-point encoding format for BF1CVTLT is selected by FPMR.F8S1. The 8-bit floating-point encoding format for BF2CVTLT is selected by FPMR.F8S2.

This instruction is unpredicated.

It has encodings from 2 classes: BF1CVTLT and BF2CVTLT

### BF1CVTLT
(FEAT_FP8)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | Zn | Zd
| L |  |  |  |  |

####

BF1CVTLT <Zd>.H, <Zn>.B

if (!HaveSVE2() && !HaveSME2()) || !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; constant integer esize = 16; integer n = UInt(Zn); integer d = UInt(Zd); boolean issrc2 = FALSE;

### BF2CVTLT
(FEAT_FP8)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | Zn | Zd
| L |  |  |  |  |

####

BF2CVTLT <Zd>.H, <Zn>.B

if (!HaveSVE2() && !HaveSME2()) || !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; constant integer esize = 16; integer n = UInt(Zn); integer d = UInt(Zd); boolean issrc2 = TRUE;

### Assembler Symbols

<Zd> | Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Zn> | Is the name of the source scalable vector register, encoded in the "Zn" field.

### Operation

CheckFPMREnabled(); CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV esize; bits(VL) operand = Z[n, VL]; bits(VL) result; for e = 0 to elements-1 bits(esize DIV 2) element = Elem[operand, 2*e + 1, esize DIV 2]; Elem[result, e, esize] = FP8ConvertBF(element, issrc2, FPCR, FPMR); Z[d, VL] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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