Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## DUP (indexed)

Broadcast indexed element to vector (unpredicated)

Unconditionally broadcast the indexed source vector element into each element of the destination vector. This instruction is unpredicated.

The immediate element index is in the range of 0 to 63 (bytes), 31 (halfwords), 15 (words), 7 (doublewords) or 3 (quadwords). Selecting an element beyond the accessible vector length causes the destination vector to be set to zero.

This instruction is used by the alias MOV (SIMD&FP scalar, unpredicated).

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | imm2 | 1 | tsz | 0 | 0 | 1 | 0 | 0 | 0 | Zn | Zd

####

DUP <Zd>.<T>, <Zn>.<T>[<imm>]

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; if tsz == '00000' then UNDEFINED; constant integer lsb = LowestSetBit(tsz); constant integer esize = 8 << lsb; constant bits(7) imm = imm2:tsz; constant integer index = UInt(imm<6:(lsb+1)>); constant integer n = UInt(Zn); constant integer d = UInt(Zd);

### Assembler Symbols

<Zd> | Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T> | Is the size specifier, encoded in tsz:
tsz | <T>
--- | ---
00000 | RESERVED
xxxx1 | B
xxx10 | H
xx100 | S
x1000 | D
10000 | Q

<Zn> | Is the name of the source scalable vector register, encoded in the "Zn" field.

<imm> | Is the immediate index, in the range 0 to one less than the number of elements in 512 bits, encoded in "imm2:tsz".

### Alias Conditions

Alias | Is preferred when
--- | ---
MOV (SIMD&FP scalar, unpredicated) | BitCount(imm2:tsz) == 1
MOV (SIMD&FP scalar, unpredicated) | BitCount(imm2:tsz) > 1

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(VL) operand1 = Z[n, VL]; bits(VL) result; bits(esize) element; if index >= elements then element = Zeros(esize); else element = Elem[operand1, index, esize]; result = Replicate(element, VL DIV esize); Z[d, VL] = result;

### Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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