Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## SM3SS1

SM3SS1 rotates the top 32 bits of the 128-bit vector in the first source SIMD&FP register by 12, and adds that 32-bit value to the two other 32-bit values held in the top 32 bits of each of the 128-bit vectors in the second and third source SIMD&FP registers, rotating this result left by 7 and writing the final result into the top 32 bits of the vector in the destination SIMD&FP register, with the bottom 96 bits of the vector being written to 0.

This instruction is implemented only when FEAT_SM3 is implemented.

### Advanced SIMD
(FEAT_SM3)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | Rm | 0 | Ra | Rn | Rd

####

SM3SS1 <Vd>.4S, <Vn>.4S, <Vm>.4S, <Va>.4S

if !HaveSM3Ext() then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); integer a = UInt(Ra);

### Assembler Symbols

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn> | Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm> | Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

<Va> | Is the name of the third SIMD&FP source register, encoded in the "Ra" field.

### Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(128) Vm = V[m, 128]; bits(128) Vn = V[n, 128]; bits(128) Va = V[a, 128]; bits(128) result; result<127:96> = ROL((ROL(Vn<127:96>, 12) + Vm<127:96> + Va<127:96>), 7); result<95:0> = Zeros(96); V[d, 128] = result;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.