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# AT S1E3W, Address Translate Stage 1 EL3 Write

The AT S1E3W characteristics are:

## Purpose

Performs stage 1 address translation as defined for EL3, with permissions as if writing to the given virtual address.

## Configuration

There are no configuration notes.

## Attributes

AT S1E3W is a 64-bit System instruction.

## Field descriptions

63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
Input address for translation
Input address for translation

#### Bits [63:0]

Input address for translation. The resulting address can be read from the PAR_EL1.

If the address translation instructions are targeting a translation regime that is using AArch32, and so has a VA of only 32 bits, then VA[63:32] is RES0.

## Executing AT S1E3W

Accesses to this instruction use the following encodings in the System instruction encoding space:

#### AT S1E3W, <Xt>

op0 | op1 | CRn | CRm | op2
--- | --- | --- | --- | ---
0b01 | 0b110 | 0b0111 | 0b1000 | 0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then UNDEFINED; elsif PSTATE.EL == EL2 then UNDEFINED; elsif PSTATE.EL == EL3 then AArch64.AT(X[t, 64], TranslationStage_1, EL3, ATAccess_Write);

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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