Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## UQCVTN

Unsigned saturating extract narrow and interleave

Saturate the unsigned integer value in each element of the group of two source vectors to half the orginal source element width, and place the two-way interleaved results in the half-width destination elements.

This instruction is unpredicated.

### SVE2
(FEAT_SVE2p1)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | Zn | 0 | Zd
| tszh |  | tszl<1> | tszl<0> |  |  | U |  |  |  |

####

UQCVTN <Zd>.H, { <Zn1>.S-<Zn2>.S }

if !HaveSME2() && !HaveSVE2p1() then UNDEFINED; constant integer esize = 16; integer n = UInt(Zn:'0'); integer d = UInt(Zd);

### Assembler Symbols

<Zd> | Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Zn1> | Is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 2.

<Zn2> | Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" times 2 plus 1.

### Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV (2 * esize); bits(VL) result; for e = 0 to elements-1 for i = 0 to 1 bits(VL) operand = Z[n+i, VL]; integer element = UInt(Elem[operand, e, 2 * esize]); Elem[result, 2*e + i, esize] = UnsignedSat(element, esize); Z[d, VL] = result;

### Operational information

When PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

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