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# CTIITCTRL, CTI Integration mode Control register

The CTIITCTRL characteristics are:

## Purpose

Enables the CTI to switch from its default mode into integration mode, where test software can control directly the inputs and outputs of the PE, for integration testing or topology detection.

## Configuration

The power domain of CTIITCTRL is IMPLEMENTATION DEFINED.

Implementation of this register is OPTIONAL.

## Attributes

CTIITCTRL is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | IME

#### Bits [31:1]

Reserved, RES0.

#### IME, bit [0]

Integration mode enable. When IME == 1, the device reverts to an integration mode to enable integration testing or topology detection.

IME | Meaning
--- | ---
0b0 | Normal operation.
0b1 | Integration mode enabled.

The integration mode behavior is IMPLEMENTATION DEFINED.

The following resets apply:

- If the register is implemented in the Core power domain:

  - On a Cold reset, this field resets to 0.

  - On an External debug reset, the value of this field is unchanged.

  - On a Warm reset, the value of this field is unchanged.

- If the register is implemented in the External debug power domain:

  - On a Cold reset, the value of this field is unchanged.

  - On an External debug reset, this field resets to 0.

  - On a Warm reset, the value of this field is unchanged.

## Accessing CTIITCTRL

#### CTIITCTRL can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
CTI | 0xF00 | CTIITCTRL

This interface is accessible as follows:

- When DoubleLockStatus(), or !IsCorePowered() or OSLockStatus(), accesses to this register are IMPDEF.
- When SoftwareLockStatus(), accesses to this register are RO.
- Otherwise, accesses to this register are RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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