Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## DUP (element)

Duplicate vector element to vector or scalar. This instruction duplicates the vector element at the specified element index in the source SIMD&FP register into a scalar or each element in a vector, and writes the result to the destination SIMD&FP register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

This instruction is used by the alias MOV (scalar).

It has encodings from 2 classes: Scalar and Vector

### Scalar

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | 0 | 0 | 0 | 0 | 1 | Rn | Rd

####

DUP <V><d>, <Vn>.<T>[<index>]

integer d = UInt(Rd); integer n = UInt(Rn); integer size = LowestSetBit(imm5); if size > 3 then UNDEFINED; integer index = UInt(imm5<4:size+1>); integer idxdsize = if imm5<4> == '1' then 128 else 64; integer esize = 8 << size; integer datasize = esize; integer elements = 1;

### Vector

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | 0 | 0 | 0 | 0 | 1 | Rn | Rd

####

DUP <Vd>.<T>, <Vn>.<Ts>[<index>]

integer d = UInt(Rd); integer n = UInt(Rn); integer size = LowestSetBit(imm5); if size > 3 then UNDEFINED; integer index = UInt(imm5<4:size+1>); integer idxdsize = if imm5<4> == '1' then 128 else 64; if size == 3 && Q == '0' then UNDEFINED; integer esize = 8 << size; integer datasize = if Q == '1' then 128 else 64; integer elements = datasize DIV esize;

### Assembler Symbols

<T> | For the scalar variant: is the element width specifier, encoded in imm5:
imm5 | <T>
--- | ---
x0000 | RESERVED
xxxx1 | B
xxx10 | H
xx100 | S
x1000 | D
| For the vector variant: is an arrangement specifier, encoded in imm5:Q:
imm5 | Q | <T>
--- | --- | ---
x0000 | x | RESERVED
xxxx1 | 0 | 8B
xxxx1 | 1 | 16B
xxx10 | 0 | 4H
xxx10 | 1 | 8H
xx100 | 0 | 2S
xx100 | 1 | 4S
x1000 | 0 | RESERVED
x1000 | 1 | 2D

<Ts> | Is an element size specifier, encoded in imm5:
imm5 | <Ts>
--- | ---
x0000 | RESERVED
xxxx1 | B
xxx10 | H
xx100 | S
x1000 | D

<V> | Is the destination width specifier, encoded in imm5:
imm5 | <V>
--- | ---
x0000 | RESERVED
xxxx1 | B
xxx10 | H
xx100 | S
x1000 | D

<Vn> | Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<index> | Is the element index encoded in imm5:
imm5 | <index>
--- | ---
x0000 | RESERVED
xxxx1 | imm5<4:1>
xxx10 | imm5<4:2>
xx100 | imm5<4:3>
x1000 | imm5<4>

<d> | Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

### Operation

CheckFPAdvSIMDEnabled64(); bits(idxdsize) operand = V[n, idxdsize]; bits(datasize) result; bits(esize) element; element = Elem[operand, index, esize]; for e = 0 to elements-1 Elem[result, e, esize] = element; V[d, datasize] = result;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.53, AdvSIMD v29.11, pseudocode v2022-09_rel, sve v2022-09_rel ; Build timestamp: 2022-09-30T16:37

Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.