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# TRCRSR, Trace Resources Status Register

The TRCRSR characteristics are:

## Purpose

Use this to set, or read, the status of the resources.

## Configuration

External register TRCRSR bits [31:0] are architecturally mapped to AArch64 System register TRCRSR[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCRSR are RES0.

## Attributes

TRCRSR is a 32-bit register.

## Field descriptions

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RES0 | TA | EVENT[3] | EVENT[2] | EVENT[1] | EVENT[0] | RES0 | EXTIN[3] | EXTIN[2] | EXTIN[1] | EXTIN[0]

#### Bits [31:13]

Reserved, RES0.

#### TA, bit [12]

Tracing active.

TA | Meaning
--- | ---
0b0 | Tracing is not active.
0b1 | Tracing is active.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

#### EVENT[<m>], bit [m+8], for m = 3 to 0

Untraced status of ETEEvents.

EVENT[<m>] | Meaning
--- | ---
0b0 | An ETEEvent <m> has not occurred.
0b1 | An ETEEvent <m> has occurred while the resources were in the Paused state.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

- When TRCIDR4.NUMRSPAIR == 0b0000, access to this field is RES0 .
- Access is RES0 if TRCIDR4.NUMRSPAIR != 0b0000 and m > UInt(TRCIDR0.NUMEVENT).
- Otherwise, access to this field is RW.

#### Bits [7:4]

Reserved, RES0.

#### EXTIN[<m>], bit [m], for m = 3 to 0

The sticky status of the External Input Selectors.

EXTIN[<m>] | Meaning
--- | ---
0b0 | An event selected by External Input Selector <m> has not occurred.
0b1 | At least one event selected by External Input Selector <m> has occurred while the resources were in the Paused state.

The reset behavior of this field is:

- On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

- When m >= UInt(TRCIDR5.NUMEXTINSEL), access to this field is RES0 .
- Otherwise, access to this field is RW.

## Accessing TRCRSR

Must always be programmed.

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

Reads from this register might return an UNKNOWN value if the trace unit is not in either of the Idle or Stable states.

#### TRCRSR can be accessed through the external debug interface:

Component | Offset | Instance
--- | --- | ---
ETE | 0x028 | TRCRSR

This interface is accessible as follows:

- When OSLockStatus(), or !AllowExternalTraceAccess() or !IsTraceCorePowered(), accesses to this register generate an error response.
- Otherwise, accesses to this register are RW.

AArch32 Registers | AArch64 Registers | AArch32 Instructions | AArch64 Instructions | Index by Encoding | External Registers | External Registers by Offset | Registers by Functional Group | Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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