Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## DUP (general)

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | imm5 | 0 | 0 | 0 | 0 | 1 | 1 | Rn | Rd

####

DUP <Vd>.<T>, <R><n>

integer d = UInt(Rd); integer n = UInt(Rn); integer size = LowestSetBit(imm5); if size > 3 then UNDEFINED; // imm5<4:size+1> is IGNORED if size == 3 && Q == '0' then UNDEFINED; constant integer esize = 8 << size; constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize;

### Assembler Symbols

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T> | Is an arrangement specifier, encoded in imm5:Q:
imm5 | Q | <T>
--- | --- | ---
x0000 | x | RESERVED
xxxx1 | 0 | 8B
xxxx1 | 1 | 16B
xxx10 | 0 | 4H
xxx10 | 1 | 8H
xx100 | 0 | 2S
xx100 | 1 | 4S
x1000 | 0 | RESERVED
x1000 | 1 | 2D

<R> | Is the width specifier for the general-purpose source register, encoded in imm5:
imm5 | <R>
--- | ---
x0000 | RESERVED
xxxx1 | W
xxx10 | W
xx100 | W
x1000 | X
Unspecified bits in "imm5" are ignored but should be set to zero by an assembler.

<n> | Is the number [0-30] of the general-purpose source register or ZR (31), encoded in the "Rn" field.

### Operation

CheckFPAdvSIMDEnabled64(); bits(esize) element = X[n, esize]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = element; V[d, datasize] = result;

### Operational information

If PSTATE.DIT is 1:

- The execution time of this instruction is independent of:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.
- The response of this instruction to asynchronous exceptions does not vary based on:
  - The values of the data supplied in any of its registers.
  - The values of the NZCV flags.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.74, AdvSIMD v29.23, pseudocode v2023-09_rel, sve v2023-09_rc3 ; Build timestamp: 2023-09-27T17:06

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