Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## FCVTN, FCVTN2 (double to single-precision, single to half-precision)

Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR.

FCVTN writes the vector to the lower half of the destination register and clears the upper half. FCVTN2 writes the vector to the upper half of the destination register without affecting the other bits of the register.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the Security state and Exception level in which the instruction is executed, an attempt to execute the instruction might be trapped.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 0 | sz | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | Rn | Rd
|  | U |  |  |  | opcode |  |  |

####

FCVTN{2} <Vd>.<Tb>, <Vn>.<Ta>

integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 16 << UInt(sz); constant integer datasize = 64; integer part = UInt(Q); integer elements = datasize DIV esize;

### Assembler Symbols

2 | Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is encoded in Q:
Q | 2
--- | ---
0 | [absent]
1 | [present]

<Vd> | Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Tb> | Is an arrangement specifier, encoded in sz:Q:
sz | Q | <Tb>
--- | --- | ---
0 | 0 | 4H
0 | 1 | 8H
1 | 0 | 2S
1 | 1 | 4S

<Vn> | Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<Ta> | Is an arrangement specifier, encoded in sz:
sz | <Ta>
--- | ---
0 | 4S
1 | 2D

### Operation

CheckFPAdvSIMDEnabled64(); bits(2*datasize) operand = V[n, 2*datasize]; bits(datasize) result; for e = 0 to elements-1 Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR, esize); Vpart[d, part, datasize] = result;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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