Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## FCVT (widening)

Multi-vector floating-point convert from half-precision to single-precision (in-order)

Convert to single-precision from half-precision, each element of the source vector, and place the results in the double-width destination elements of the destination vectors.

This instruction follows SME2 floating-point numerical behaviors corresponding to instructions that place their results in one or more SVE Z vectors.

This instruction is unpredicated.

ID_AA64SMFR0_EL1.F16F16 indicates whether this instruction is implemented.

### SME2
(FEAT_SME_F16F16)

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | Zd | 0
|  |  | L

####

FCVT { <Zd1>.S-<Zd2>.S }, <Zn>.H

if !HaveSME2() || !IsFeatureImplemented(FEAT_SME_F16F16) then UNDEFINED; integer n = UInt(Zn); integer d = UInt(Zd:'0');

### Assembler Symbols

<Zd1> | Is the name of the first destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2.

<Zd2> | Is the name of the second destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2 plus 1.

<Zn> | Is the name of the source scalable vector register, encoded in the "Zn" field.

### Operation

CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 16; bits(VL) operand = Z[n, VL]; bits(2*VL) result; for e = 0 to elements-1 bits(16) element = Elem[operand, e, 16]; bits(32) res = FPConvertSVE(element, FPCR[], 32); Elem[result, e, 32] = res; Z[d+0, VL] = result<VL-1:0>; Z[d+1, VL] = result<2*VL-1:VL>;

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: isa v33.64, AdvSIMD v29.12, pseudocode v2023-06_rel, sve v2023-06_rel ; Build timestamp: 2023-07-04T19:42

Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.