Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

## LDR (literal, SIMD&FP)

Load SIMD&FP Register (PC-relative literal). This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from the PC value and an immediate offset.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
opc | 0 | 1 | 1 | 1 | 0 | 0 | imm19 | Rt
|  | VR |  |  |

#### 32-bit (opc == 00)

LDR <St>, <label>

#### 64-bit (opc == 01)

LDR <Dt>, <label>

#### 128-bit (opc == 10)

LDR <Qt>, <label>

integer t = UInt(Rt); if opc == '11' then UNDEFINED; constant integer size = 4 << UInt(opc); boolean nontemporal = FALSE; boolean tagchecked = FALSE; bits(64) offset = SignExtend(imm19:'00', 64);

### Assembler Symbols

<St> | Is the 32-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

<label> | Is the program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.

<Dt> | Is the 64-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

<Qt> | Is the 128-bit name of the SIMD&FP register to be loaded, encoded in the "Rt" field.

### Operation

bits(64) address = PC64 + offset; CheckFPEnabled64(); AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked); bits(size*8) data = Mem[address, size, accdesc]; V[t, size*8] = data;

### Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Base Instructions | SIMD&FP Instructions | SVE Instructions | SME Instructions | Index by Encoding | Shared Pseudocode | Proprietary Notice

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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